H01L2224/0382

Passivation Structure for Metal Pattern
20230052604 · 2023-02-16 ·

A semiconductor device and method of manufacturing the same are provided. The semiconductor device may include a substrate, a first via, a first pad, a second pad, and a first passivation layer. The first pad may be over the substrate. The second pad may be over the substrate. The second pad may be parallel to the first pad. The first passivation layer may surround the first pad and the second pad. The first passivation layer may include a first part on the first pad. The first passivation layer may include a second part on the second pad. A thickness of the first part of the first passivation layer may exceed a height of the first pad. A thickness of the second part of the first passivation layer may exceed a height of the second pad.

Repackaged integrated circuit assembly method
20180005910 · 2018-01-04 · ·

A method is provided. The method includes one or more of extracting a die from an original packaged integrated circuit, modifying the extracted die, reconditioning the modified extracted die, placing the reconditioned die into a cavity of a hermetic package base, bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base, and sealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit. Modifying the extracted die includes removing the one or more ball bonds on the one or more die pads. Reconditioning the modified extracted die includes adding a sequence of metallic layers to bare die pads of the modified extracted die. The extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die.

Solder Ball Application for Singular Die
20230055518 · 2023-02-23 · ·

A device is provided. The device includes one or more of a singular die, one of another die, a printed circuit board, and a substrate, and one or more solder balls. The singular die includes one or more reconditioned die pads, which include die pads of the singular die with a plurality of metallic layers applied. The other die, printed circuit board, and the substrate include one or more bond pads. The one or more solder balls are between the one or more reconditioned die pads and the one or more bond pads.

METHOD AND APPARATUS FOR IMPROVED WAFER COATING
20220367390 · 2022-11-17 ·

A semiconductor device comprises a metallization layer, a passivation layer disposed above the metallization layer, a copper redistribution layer disposed on the passivation layer, a second passivation layer disposed on the copper redistribution layer, and a polyimide layer disposed over the second passivation layer. The polyimide layer and the second passivation layer include a continuous gap there-through that exposes a portion of the copper redistribution layer.

TEMPORARY PASSIVATION LAYER ON A SUBSTRATE
20220359332 · 2022-11-10 ·

A substrate includes a metal component on a surface. A polymeric layer is deposited on the surface using molecular layer deposition. The polymeric layer includes a metalcone and has a thickness from 1 nm to 20 nm. The polymeric layer is stable at room temperature, but will undergo a structural change at high temperatures. The polymeric layer can be annealed to cause a structural change, which can occur during soldering.

Semiconductor structure having counductive bump with tapered portions and method of manufacturing the same

A method for fabricating a semiconductor structure is provided. The method includes: providing a semiconductor chip comprising an active surface; forming a conductive bump over the active surface of the semiconductor chip; and coupling the conductive bump to a substrate. The conductive bump includes a plurality of bump segments including a first group of bump segments and a second group of bump segments. Each bump segment has a same segment thickness in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment has a volume defined by a multiplication of the same segment thickness with an average cross-sectional area of the bump segment in a plane parallel to the active surface of the semiconductor chip. A ratio of a total volume of the first group of bump segments to a total volume of the second group of bump segments is between 0.03 and 0.8.

INTEGRATED CIRCUIT CHIP INCLUDING A PASSIVATION NITRIDE LAYER IN CONTACT WITH A HIGH VOLTAGE BONDING PAD AND METHOD OF MAKING

A back end of line (BEOL) structure for an integrated circuit chip includes a last metal structure providing a bonding pad. A passivation structure over the bonding pad includes a first opening extending exposing an upper surface of the bonding pad. A conformal nitride layer extends over the passivation structure and is placed in contact with the upper surface of the bonding pad. An insulator material layer covers the conformal nitride layer and includes a second opening that extends through both the insulator material layer and the conformal nitride layer. A foot portion of the conformal nitride layer on the upper surface of the bonding pad is self-aligned with the second opening.

OXIDATION AND CORROSION PREVENTION IN SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE ASSEMBLIES

In some aspects, the techniques described herein relate to an electronic device including: a substrate; a metallization layer, the metallization layer having: a first surface disposed on the substrate; a second surface opposite the first surface; and a corrosion-prevention implant layer disposed in the metallization layer, the corrosion-prevention implant layer extending from the second surface to a depth from the second surface in the metallization layer, the depth being less than a thickness of the metallization layer; and an electrical connector coupled with the second surface.

SEMICONDUCTOR DEVICE WITH WIRE BOND AND METHOD FOR PREPARING THE SAME
20230106386 · 2023-04-06 · ·

A semiconductor device includes a semiconductor substrate having a bonding pad, and a first dielectric layer disposed over the semiconductor substrate. A portion of the bonding pad is exposed by the first dielectric layer. The semiconductor device also includes a metal oxide layer disposed over the portion of the bonding pad, and a wire bond penetrating through the metal oxide layer to bond to the bonding pad. The portion of the bonding pad is entirely covered by the metal oxide layer and the wire bond.

Bonded assembly containing low dielectric constant bonding dielectric material

A first metal layer can be deposited over first dielectric material layers of a first substrate, and can be patterned into first bonding pads. A first low-k material layer can be formed over the first bonding pads. The first low-k material layer includes a low-k dielectric material such as a MOF dielectric material or organosilicate glass. A second semiconductor die including second bonding pads can be provided. The first bonding pads are bonded to the second bonding pads to form a bonded assembly.