H01L2224/03828

Semiconductor device bonding area including fused solder film and manufacturing method
11545452 · 2023-01-03 · ·

A semiconductor device including a semiconductor substrate including an electrode; a wire connected to the electrode; a first insulating film including a first opening that partially exposes the wire; a base portion that is connected to a portion of the wire exposed via the first opening, and that includes a conductor including a recess corresponding to the first opening; and a solder film on a surface of the base portion. Solder included in the solder film is fused by a first heat treatment, and the recess is filled with the fused solder.

Semiconductor device bonding area including fused solder film and manufacturing method
11545452 · 2023-01-03 · ·

A semiconductor device including a semiconductor substrate including an electrode; a wire connected to the electrode; a first insulating film including a first opening that partially exposes the wire; a base portion that is connected to a portion of the wire exposed via the first opening, and that includes a conductor including a recess corresponding to the first opening; and a solder film on a surface of the base portion. Solder included in the solder film is fused by a first heat treatment, and the recess is filled with the fused solder.

Method for manufacturing semiconductor device

A method for manufacturing a semiconductor device includes forming a thermosetting resin film on a first metal layer, forming an opening in the resin film, forming a second metal layer that covers a region from an upper surface of the first metal layer exposed from the opening of the resin film to an upper surface of the resin film, performing heat treatment at a temperature equal to or higher than a temperature at which the resin film is cured after forming the second metal layer, forming a cover film that covers the upper surface of the resin film and a side surface of the second metal layer after performing the heat treatment, and forming a solder on an upper surface of the second metal layer exposed from an opening of the cover film after forming the cover film.

Semiconductor package and method of fabricating the same

A semiconductor package includes a semiconductor substrate, a conductive pad on the semiconductor substrate, a redistribution line conductor, a coating insulator, and an aluminum oxide layer. The redistribution line conductor is electrically connected to the conductive pad. The coating insulator covers the redistribution line conductor and partially exposes the redistribution line conductor. The aluminum oxide layer is provided below the coating insulator and extends along a top surface of the redistribution line conductor, and the aluminum oxide layer is in contact with the redistribution line conductor.

Solder member mounting system
11583948 · 2023-02-21 · ·

A solder member mounting method includes providing a substrate having bonding pads formed thereon, detecting a pattern interval of the bonding pads, selecting one of solder member attachers having different pattern intervals from each other, such that the one selected solder member attacher of the solder member attachers has a pattern interval corresponding to the detected pattern interval of the bonding pads, and attaching solder members on the bonding pads of the substrate, respectively, using the one selected solder member attacher.

SEMICONDUCTOR DEVICE UNDER BUMP STRUCTURE AND METHOD THEREFOR

A method of manufacturing a semiconductor device is provided. The method includes depositing a non-conductive layer over a semiconductor die. An opening is formed in the non-conductive layer exposing a portion of a bond pad of the semiconductor die. A cavity is in the non-conductive layer with a portion of the non-conductive layer remaining between a bottom surface of the cavity and a bottom surface of the non-conductive layer. A conductive layer is formed over the non-conductive layer and the portion of the bond pad. The conductive layer is configured to interconnect the bond pad with a conductive layer portion over the cavity.

Semiconductor package and manufacturing method thereof

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a lower structure including a semiconductor chip having a chip terminal; an external connection terminal connecting the semiconductor chip to an external device; and an intermediate connection structure including an upper surface and a lower surface opposite to the upper surface, and positioned between the lower structure and the external connection terminal.

CONDUCTIVE BUFFER LAYERS FOR SEMICONDUCTOR DIE ASSEMBLIES AND ASSOCIATED SYSTEMS AND METHODS
20230063954 · 2023-03-02 ·

Conductive buffer layers for semiconductor die assemblies, and associated systems and methods are disclosed. In an embodiment, a semiconductor die assembly includes first and second semiconductor dies directly bonded to each other. The first semiconductor die includes a first copper pad and the second semiconductor die includes a second copper pad. The first and second copper pads form an interconnect between the first and second semiconductor dies, and the interconnect includes a conductive buffer material between the first and second copper pads, where the conductive buffer material includes aggregates of conductive particles. In some embodiments, the first and second copper pads are not conjoined but electrically connected to each other through the conductive buffer material. In some embodiments, the conductive buffer material is porous such that the aggregates of conductive particles can be compressed together in response to the pressure applied to the conductive buffer layer.

SHEET MOLDING PROCESS FOR WAFER LEVEL PACKAGING
20170372998 · 2017-12-28 ·

Discussed generally herein are methods and devices including or providing a redistribution layer device without under ball metallization. A device can include a substrate, electrical interconnect circuitry in the substrate, redistribution layer (RDL) circuitry electrically connected to the electrical interconnect circuitry, a conductive bump electrically connected to the RDL circuitry, the conductive bump interfacing directly with the RDL circuitry, and a sheet molding material over the substrate.

Method of packaging integrated circuits

Integrated circuits are packaged by placing a plurality of semiconductor dies on a support substrate, each one of the semiconductor dies having a plurality of terminals at a side facing the support substrate and covering the semiconductor dies with a molding compound to form a molded structure. The support substrate is then removed from the molded structure to expose the side of the semiconductor dies with the terminals, and a metal redistribution layer is formed on the molded structure and in direct contact with the terminals of the semiconductor dies and the molding compound. The redistribution layer is formed without first forming a dielectric layer on a side of the molded structure with the terminals of the semiconductor dies. A corresponding molded substrate and individual molded semiconductor packages are also disclosed.