A semiconductor package includes a semiconductor chip including a second bonding insulating layer surrounding at least a portion of each of a first bonding pad structure and a second bonding pad structure, in which the first bonding pad structure includes a first contact portion, a first bonding pad, and a first seed layer disposed between the first bonding pad and the first contact portion and extending in a first direction, the second bonding pad structure includes a second contact portion, a second bonding pad, and a second seed layer disposed between the second bonding pad and the second contact portion and extending in the first direction, and the second bonding insulating layer is in contact with a side surface of each of the first and second seed layers and the first and second bonding pads.

A method of treatment of an electronic circuit including at a location at least one electrically-conductive test pad having a first exposed surface. The method includes the at least partial etching of the test pad from the first surface, and the forming on the electronic circuit of an interconnection level covering said location and including, on the side opposite to said location, a second planar surface adapted for the performing of a hybrid molecular bonding.

A semiconductor package includes a first structure having a first insulating layer and a first bonding pad penetrating the first insulating layer, and a second structure on the first structure and having a second insulating layer bonded to the first insulating layer, a bonding pad structure penetrating the second insulating layer and bonded to the first bonding pad, and a test pad structure penetrating the second insulating layer and including a test pad in an opening penetrating the second insulating layer and having a protrusion with a flat surface, and a bonding layer filling the opening and covering the test pad and the flat surface, the protrusion of the test pad extending from a surface in contact with the bonding layer, and the flat surface of the protrusion being within the opening and spaced apart from an interface between the bonding layer and the first insulating layer.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region and coupled to the first microelectronic component by the first and second direct bonding regions, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, and wherein individual first metal contacts in the first direct bonding region are coupled to respective individual second metal contacts in the second direct bonding region; and a void between an individual first metal contact and a respective individual second metal contact.

A redistribution layer for an integrated circuit is made by forming a conductive interconnection layer; forming a conductive body in electrical contract with the interconnection layer; and covering the conductive body with a first coating layer having a thickness less than 100 nm. The first coating layer is configured to provide a protection against oxidation and/or corrosion of the conductive body. To carry out an electrical test of the integrated circuit, a testing probe locally perforates the first coating layer until the conductive body is electrically contacted by the testing probe.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the first microelectronic component is coupled to the second microelectronic component by interconnects, and wherein the interconnects include individual first metal contacts coupled to respective individual second metal contacts; and a void between an individual first metal contact that is not coupled to a respective individual second metal contact, wherein the void is in the first direct bonding region.

A method of packaging a semiconductor device having a bond pad on a surface thereof includes forming a redistribution material electrically coupled to the bond pad, forming a dielectric material over the redistribution material, and removing a first portion of the dielectric material to expose a first portion of the redistribution material. Semiconductor packages may include a redistribution layer having a first portion adjacent and coupled to a first contact of the package, a second portion exposed by a first opening in a dielectric material, and a redistribution line electrically coupled to a first bond pad, the first portion, and the second portion. Such a package may be tested placing at least one probe needle in contact with at least one terminal of the package, providing a test signal from the probe needle to the package through the terminal, and detecting signals using the needle.

A detection pad structure in a semiconductor device may include a lower wiring on a substrate, an upper wiring on the lower wiring, and a first pad pattern on the upper wiring. The upper wiring may be connected to the lower wiring and include metal patterns and via contacts on the metal patterns that are stacked in a plurality of layers. The first pad pattern may be connected to the upper wiring. A semiconductor device may include an actual upper wiring including actual metal patterns and actual via contacts stacked in a plurality of layers. At least one of the metal patterns of each layer in the upper wiring may have a minimum line width and a minimum space of the metal patterns of each layer in the actual upper wiring. Metal patterns and via contacts of each layer in the upper wiring may be regularly and repeatedly arranged.

According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.

A conductive terminal on an integrated circuit is provided. The conductive terminal includes a conductive pad, a dielectric layer, and a conductive via. The conductive pad is disposed on and electrically to the integrated circuit. The dielectric layer covers the integrated circuit and the conductive pad, the dielectric layer includes a plurality of contact openings arranged in array, and the conductive pad is partially exposed by the contact openings. The conductive via is disposed on the dielectric layer and electrically connected to the conductive pad through the contact openings. The conductive via includes a plurality of convex portions arranged in array. The convex portions are distributed on a top surface of the conductive via, and the convex portions are corresponding to the contact openings.