A solder pad includes a surface. A tin layer is arranged on the surface. At least one out of a bismuth layer, an antimony layer and a nickel layer is arranged on the tin layer.

A semiconductor package includes a semiconductor substrate, a conductive pad on the semiconductor substrate, a redistribution line conductor, a coating insulator, and an aluminum oxide layer. The redistribution line conductor is electrically connected to the conductive pad. The coating insulator covers the redistribution line conductor and partially exposes the redistribution line conductor. The aluminum oxide layer is provided below the coating insulator and extends along a top surface of the redistribution line conductor, and the aluminum oxide layer is in contact with the redistribution line conductor.

A wafer includes a substrate and conductive bumps on a surface of the substrate. In a plan view from a direction perpendicular to the surface of the substrate, the area density of the conductive bumps is higher in a first area than in a second area around the first area in the surface of the substrate. The first area has effective chip areas arranged therein.

A power semiconductor device includes a semiconductor body and a first terminal at the semiconductor body. The first terminal has a first side for adjoining an encapsulation and a second side for adjoining the semiconductor body. The first terminal includes, at the first side, a top layer; and, at the second side, a base layer coupled with the top layer, wherein a sidewall of the top layer and/or a sidewall of the base layer is arranged in an angle smaller than 85° with respect to a plane.

A method includes forming a first electrode layer having a first opening, with the first opening having a first lateral dimension, forming a first capacitor insulator over the first electrode layer, and forming a second electrode layer over the first capacitor insulator, with the second electrode layer having a second opening. The first opening is directly underlying the second opening. The second opening has a second lateral dimension greater than the first lateral dimension. The method further includes depositing a dielectric layer over the second electrode layer, and forming a contact opening, which comprises a first portion including the first opening, and a second portion including the second opening. A conductive plug is formed in the contact opening.

A power semiconductor chip having: a semiconductor component body; a multilayer metallization arranged on the semiconductor component body; and a nickel layer arranged over the semiconductor component body. The invention further relates to a method for producing a power semiconductor chip and to a power semiconductor device. The invention provides a power semiconductor chip which has a metallization to which a copper wire, provided without a thick metallic coating, can be reliably bonded without damage to the power semiconductor chip during bonding.

A light emitting apparatus includes at least one light emitting device; a light transparent member that receives incident light emitted from the light emitting device; and a covering member. The light transparent member is a light conversion member that has an externally exposed light emission surface and a side surface contiguous to the light emission surface. The covering member contains a light reflective material, and covers at least the side surface of said light transparent member. A content of said light reflective material is not less than 30 wt %.

A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature.

Compression cold welding methods, joint structures, and hermetically sealed containment devices are provided. The method includes providing a first substrate having at least one first joint structure which comprises a first joining surface, which surface comprises a first metal; providing a second substrate having at least one second joint structure which comprises a second joining surface, which surface comprises a second metal; and compressing together the at least one first joint structure and the at least one second joint structure to locally deform and shear the joining surfaces at one or more interfaces in an amount effective to form a metal-to-metal bond between the first metal and second metal of the joining surfaces. Overlaps at the joining surfaces are effective to displace surface contaminants and facilitate intimate contact between the joining surfaces without heat input. Hermetically sealed devices can contain drug formulations, biosensors, or MEMS devices.

A light emitting apparatus includes: a mount substrate; a first light emitting device mounted on the mount substrate; a light transparent member, wherein a lower surface of the light transparent member is attached to an upper surface of the first light emitting device via an adhesive material, wherein the light transparent member has a plate shape and is positioned to receive incident light emitted from the first light emitting device, and wherein a first lateral surface of the light transparent member is located laterally inward of a lateral surface of the first light emitting device; and a covering member that contains a light reflective material and covers at least the lateral surface of the light transparent member.