Patent classifications
H01L2224/0502
Integrated circuit packages and methods for forming the same
A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.
Semiconductor Device Having Through Silicon Vias and Manufacturing Method Thereof
In the semiconductor device, a semiconductor substrate has first and second surfaces. A circuitry layer is formed over the first surface and a first insulating layer is further formed over the circuitry layer. A second insulating layer including a first insulating element is formed over the second surface. A third insulating layer including a second insulating element different from the first insulating element of the second insulating layer is formed over the second surface with an intervention of the second insulating layer therebetween. A penetration electrode penetrates through the semiconductor substrate, the circuitry layer, the first insulating layer, the second insulating layer and the third insulating layer.
MULTI-CHIP MODULE INCLUDING STANDALONE CAPACITORS
In some examples, a multi-chip module (MCM), comprises a first and a second die-attach pad (DAP); a first die comprising a first set of microelectronic devices; a second die comprising a first capacitor and a second capacitor; and a third die comprising a second set of microelectronic devices, where the first and second dies are positioned on the first DAP, and the third die is positioned on the second DAP. The first set of microelectronic devices couples to the first capacitor via a first inter-die connection and the second set of microelectronic devices couples to the second capacitor via a second inter-die connection.
Method of forming a semiconductor device having through silicon vias
In the semiconductor device, a semiconductor substrate has first and second surfaces. A circuitry layer is formed over the first surface and a first insulating layer is further formed over the circuitry layer. A second insulating layer including a first insulating element is formed over the second surface. A third insulating layer including a second insulating element different from the first insulating element of the second insulating layer is formed over the second surface with an intervention of the second insulating layer therebetween. A penetration electrode penetrates through the semiconductor substrate, the circuitry layer, the first insulating layer, the second insulating layer and the third insulating layer.
Integrated Circuit Packages and Methods for Forming the Same
A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.
CHIP PARTS AND METHOD FOR MANUFACTURING THE SAME, CIRCUIT ASSEMBLY HAVING THE CHIP PARTS AND ELECTRONIC DEVICE
A chip part according to the present invention includes a substrate having a penetrating hole, a pair of electrodes formed on a front surface of the substrate and including one electrode overlapping the penetrating hole in a plan view and another electrode facing the one electrode, and an element formed on the front surface side of the substrate and electrically connected to the pair of electrodes.
CHIP PARTS AND METHOD FOR MANUFACTURING THE SAME, CIRCUIT ASSEMBLY HAVING THE CHIP PARTS AND ELECTRONIC DEVICE
A chip part according to the present invention includes a substrate having a penetrating hole, a pair of electrodes formed on a front surface of the substrate and including one electrode overlapping the penetrating hole in a plan view and another electrode facing the one electrode, and an element formed on the front surface side of the substrate and electrically connected to the pair of electrodes.
Integrated circuit packages and methods for forming the same
A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.
ELECTRONIC SUBSTRATE AND ELECTRONIC DEVICE
An electronic substrate and an electronic device are provided. The electronic substrate includes a base, a conductive electrode, and a first layer. The conductive electrode and the first layer are disposed on the base, the first layer surrounds the conductive electrode and overlaps an edge portion of the conductive electrode. In a cross-sectional view, the first layer is divided into a first part and a second part, the conductive electrode is located between the first part and the second part, and a width of the first part is different from a width of the second part.
Semiconductor device having through silicon vias and manufacturing method thereof
In The semiconductor device, a semiconductor substrate has first and second surfaces. A circuitry layer is formed over the first surface and a first insulating layer is further formed over the circuitry layer. A second insulating layer including a first insulating element is formed over the second surface. A third insulating layer including a second insulating element different from the first insulating element of the second insulating layer is formed over the second surface with an intervention of the second insulating layer therebetween. A penetration electrode penetrates through the semiconductor substrate, the circuitry layer, the first insulating layer, the second insulating layer and the third insulating layer.