A cryo-compatible quantum computing arrangement includes a microelectronic quantum computing component having a substrate structure, a plurality of first contact elements and a plurality of conductive feedthroughs through the substrate structure, wherein the conductive feedthroughs are electrically connected on a first main surface area of the substrate structure to associated first contact elements of the microelectronic quantum computing component, and a further microelectronic component having a plurality of second contact elements, wherein on a second main surface area of the substrate structure, the conductive feedthroughs are electrically connected to associated second contact elements of the further microelectronic component, and wherein the conductive feedthroughs each include, between the first and second contact elements, a layer element including a first material that is superconducting at a quantum computing operating temperature, and a filling element including a second material that is electrically conductive.

A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes an interconnect structure on a substrate; a passivation layer disposed on the interconnect structure; a first via, a second via and a third via disposed in the passivation layer and connected to the interconnect structure, each of the first, second and third vias has an elongated shape longitudinally oriented along a first direction; and a first pad longitudinally oriented along the first direction and landing on the first, second and third vias.

A semiconductor package including a first stack; a plurality of TSVs passing through the first stack; a second stack on the first stack and including a second surface facing a first surface of the first stack; a first pad on the first stack and in contact with the TSVs; a second pad on the second stack; a bump connecting the first and second pads; a first redundancy pad on the first surface of the first stack, spaced apart from the first pad, and not in contact with the TSVs; a second redundancy pad on the second surface of the second stack and spaced apart from the second pad; and a redundancy bump connecting the first redundancy pad and the second redundancy pad, wherein the first pad and first redundancy pad are electrically connected to each other, and the second pad and second redundancy pad are electrically connected to each other.

A semiconductor device includes first conductive films that are provided, above a semiconductor substrate, at least on both sides of a non-formation region in which the first conductive films are not provided; an interlayer dielectric film including a first portion that is provided on the non-formation region, second portions provided above the first conductive film on both sides of the non-formation region, and a step portion that connects the first portion and the second portions; a second conductive film provided above the interlayer dielectric film; through terminal portions that penetrate the second portions of the interlayer dielectric film; and a wire bonded with the second conductive film above the first portion, where the through terminal portions include one or more first through terminal portions and one or more second through terminal portions being provided at positions opposite to each other with a bonded portion of the wire being interposed therebetween.

A semiconductor package including a first stack; a plurality of TSVs passing through the first stack; a second stack on the first stack and including a second surface facing a first surface of the first stack; a first pad on the first stack and in contact with the TSVs; a second pad on the second stack; a bump connecting the first and second pads; a first redundancy pad on the first surface of the first stack, spaced apart from the first pad, and not in contact with the TSVs; a second redundancy pad on the second surface of the second stack and spaced apart from the second pad; and a redundancy bump connecting the first redundancy pad and the second redundancy pad, wherein the first pad and first redundancy pad are electrically connected to each other, and the second pad and second redundancy pad are electrically connected to each other.

A semiconductor package includes a first semiconductor chip including a first substrate and a first bonding layer disposed on the first substrate, and having a flat first outer surface provided by the first bonding layer; and a second semiconductor chip disposed on the first outer surface of the first semiconductor chip, including a second substrate and a second bonding layer disposed on the second substrate, and having a flat second outer surface provided by the second bonding layer and contacting the first outer surface of the first semiconductor chip. The first bonding layer includes a first outermost insulating layer providing the first outer surface, a first internal insulating layer stacked between the first outermost insulating layer and the first substrate, first external marks disposed in the first outermost insulating layer and spaced apart from each other, and first internal marks interlaced with the first external marks within the first internal insulating layer.

A method of manufacturing a semiconductor chip is provided. The method includes: forming a plurality of bonding pads on a semiconductor wafer, sequentially forming an insulating layer and a polishing stop film on the semiconductor wafer to cover the plurality of bonding pads, the insulating layer and the polishing stop film having a plurality of convex portions corresponding to upper portions of the plurality of bonding pads, polishing the plurality of convex portions using the polishing stop film to expose upper surfaces of the plurality of bonding pads, and removing the polishing stop film.

A semiconductor package includes a first semiconductor chip including a first semiconductor layer, a first through-electrode that penetrates through the first semiconductor layer, a first bonding pad connected to the first through-electrode, and a first insulating bonding layer, and a second semiconductor chip on the first semiconductor chip and including a second semiconductor layer, a second bonding pad bonded to the first bonding pad, and a second insulating bonding layer bonded to the first insulating bonding layer, wherein the first insulating bonding layer includes a first insulating material, the second insulating bonding layer includes a first insulating layer that forms a bonding interface with the first insulating bonding layer and a second insulating layer on the first insulating layer, the first insulating layer includes a second insulating material, different from the first insulating material, and the second insulating layer includes a third insulating material, different from the second insulating material.

A semiconductor memory device including a substrate, first pad layers and a second pad layer on the substrate, a pattern structure including first openings on the first pad layers and a second opening on the second pad layer, and having first and second regions, gate electrodes on the pattern structure and each including a pad region, channel structures penetrating through the gate electrodes in the first region, gate contact plugs electrically connected to the gate electrodes through the pad region of each of the gate electrodes and extending in a vertical direction to penetrate the first openings and connected to the first pad layers, a source contact plug, extending in the vertical direction penetrating the second opening and connected to the second pad layer, and a source connection patter under the pattern structure and in contact with the source contact plug and the second pad layer may be provided.

A semiconductor device includes first conductive films that are provided, above a semiconductor substrate, at least on both sides of a non-formation region in which the first conductive films are not provided; an interlayer dielectric film including a first portion that is provided on the non-formation region, second portions provided above the first conductive film on both sides of the non-formation region, and a step portion that connects the first portion and the second portions; a second conductive film provided above the interlayer dielectric film; through terminal portions that penetrate the second portions of the interlayer dielectric film; and a wire bonded with the second conductive film above the first portion, where the through terminal portions include one or more first through terminal portions and one or more second through terminal portions being provided at positions opposite to each other with a bonded portion of the wire being interposed therebetween.