Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

A cobalt electroplating composition may include (a) cobalt ions; and (b) an ammonium compound of formula (NR.sup.1R.sup.2R.sup.3H.sup.+).sub.nX.sup.n−, wherein R.sup.1, R.sup.2, R.sup.3 are independently H or linear or branched C.sub.1 to C.sub.6 alkyl, X is one or more n valent inorganic or organic counter ion(s), and n is an integer from 1, 2, or 3.

A cobalt electroplating composition may include (a) cobalt ions; and (b) an ammonium compound of formula (NR.sup.1R.sup.2R.sup.3H.sup.+).sub.nX.sup.n−, wherein R.sup.1, R.sup.2, R.sup.3 are independently H or linear or branched C.sub.1 to C.sub.6 alkyl, X is one or more n valent inorganic or organic counter ion(s), and n is an integer from 1, 2, or 3.

A display device includes a base layer; a pixel circuit layer disposed on the base layer, the pixel circuit layer including a first transistor; and an insulating layer overlapping the first transistor; a first electrode disposed on the pixel circuit layer, the first electrode electrically connected to the first transistor via a contact hole of the insulating layer; a cover layer disposed on the first electrode, the cover layer overlapping at least a portion of the first electrode; a light emitting element including a first end and a second end electrically connected to the first electrode; a second electrode disposed on the light emitting element, the second electrode electrically connected to the second end of the light emitting element; and a third electrode disposed on the cover layer, the third electrode electrically contacting at least a portion of the first electrode.

A semiconductor device and a semiconductor package including the same are provided. The semiconductor device includes a semiconductor element; a protective layer disposed adjacent to the surface of the semiconductor element, the protective layer defining an opening to expose the semiconductor element; a first bump disposed on the semiconductor element; and a second bump disposed onto the surface of the protective layer. The first bump has a larger cross-section surface area than the second bump.

A semiconductor device and a semiconductor package including the same are provided. The semiconductor device includes a semiconductor element; a protective layer disposed adjacent to the surface of the semiconductor element, the protective layer defining an opening to expose the semiconductor element; a first bump disposed on the semiconductor element; and a second bump disposed onto the surface of the protective layer. The first bump has a larger cross-section surface area than the second bump.

A bonded assembly includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes first metallic bonding pads embedded in first dielectric material layers, the second semiconductor die includes second metallic bonding pads embedded in second dielectric material layers, the first metallic bonding pads are bonded to a respective one of the second metallic bonding pads; and each of the first metallic bonding pads includes a corrosion barrier layer containing an alloy of a primary bonding metal and at least one corrosion-suppressing element that is different from the primary bonding metal.

A semiconductor package includes a first semiconductor component, a second semiconductor component, and a connecting element. The first semiconductor component includes a first substrate, and a first bonding pad disposed adjacent to a first surface of the first substrate, and at least one conductive via structure extending from a second surface of the first substrate to the first bonding pad. The second semiconductor component includes a second substrate, a redistribution layer disposed adjacent to a first surface of the second substrate, and a second bonding pad disposed on the redistribution layer. The connecting element is disposed between the first bonding pad and the second bonding pad.