A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

A method of packaging a semiconductor device having a bond pad on a surface thereof includes forming a redistribution material electrically coupled to the bond pad, forming a dielectric material over the redistribution material, and removing a first portion of the dielectric material to expose a first portion of the redistribution material. Semiconductor packages may include a redistribution layer having a first portion adjacent and coupled to a first contact of the package, a second portion exposed by a first opening in a dielectric material, and a redistribution line electrically coupled to a first bond pad, the first portion, and the second portion. Such a package may be tested placing at least one probe needle in contact with at least one terminal of the package, providing a test signal from the probe needle to the package through the terminal, and detecting signals using the needle.

A method of packaging a semiconductor device having a bond pad on a surface thereof includes forming a redistribution material electrically coupled to the bond pad, forming a dielectric material over the redistribution material, and removing a first portion of the dielectric material to expose a first portion of the redistribution material. Semiconductor packages may include a redistribution layer having a first portion adjacent and coupled to a first contact of the package, a second portion exposed by a first opening in a dielectric material, and a redistribution line electrically coupled to a first bond pad, the first portion, and the second portion. Such a package may be tested placing at least one probe needle in contact with at least one terminal of the package, providing a test signal from the probe needle to the package through the terminal, and detecting signals using the needle.

A structure including an Sn layer or an Sn alloy layer includes a substrate, an Sn layer or Sn alloy layer formed above the substrate, and an under barrier metal formed between the substrate and the Sn layer or Sn alloy layer. The under barrier metal is an Ni alloy layer containing Ni, and at least one selected from W, Ir, Pt, Au, and Bi, and can sufficiently inhibit generation of an intermetallic compound through a reaction, caused due to metal diffusion of a metal contained in the substrate, between the metal and Sn contained in the Sn layer or Sn alloy layer.

A semiconductor package includes a first semiconductor chip on a lower structure. A first underfill is between the first semiconductor chip and the lower structure. The first underfill includes a first portion adjacent to a center region of the first semiconductor chip, and a second portion adjacent to an edge region of the first semiconductor chip. The second portion has a higher degree of cure than the first portion. A plurality of inner connection terminals is between the first semiconductor chip and the lower structure. The plurality of inner connection terminals extends in the first underfill.

There is provided a connection structure of a circuit member including: a first circuit member having a first main surface provided with a first electrode; a second circuit member having a second main surface provided with a second electrode; and a joining portion which is interposed between the first main surface and the second main surface, in which the joining portion has a solder portion which electrically connects the first electrode and the second electrode to each other, in which the solder portion contains a bismuth-indium alloy, and in which an amount of bismuth contained in the bismuth-indium alloy exceeds 20% by mass and is equal to or less than 80% by mass.

There is provided a connection structure of a circuit member including: a first circuit member having a first main surface provided with a first electrode; a second circuit member having a second main surface provided with a second electrode; and a joining portion which is interposed between the first main surface and the second main surface, in which the joining portion has a solder portion which electrically connects the first electrode and the second electrode to each other, in which the solder portion contains a bismuth-indium alloy, and in which an amount of bismuth contained in the bismuth-indium alloy exceeds 20% by mass and is equal to or less than 80% by mass.

According to various embodiments, a method for processing an electronic component including at least one electrically conductive contact region may include: forming a contact pad including a self-segregating composition over the at least one electrically conductive contact region to electrically contact the electronic component; forming a segregation suppression structure between the contact pad and the electronic component, wherein the segregation suppression structure includes more nucleation inducing topography features than the at least one electrically conductive contact region for perturbing a chemical segregation of the self-segregating composition by crystallographic interfaces of the contact pad defined by the nucleation inducing topography features.

A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.