A method of forming a semiconductor device includes providing a carrier comprising a die attach pad, providing a semiconductor die that includes a bond pad disposed on a main surface of the semiconductor die, and providing a metal interconnect element, arranging the semiconductor die on the die attach pad such that the bond pad faces away from the die attach pad, and welding the metal interconnect element to the bond pad, wherein the bond pad comprises first and second metal layers, wherein the second metal layer is disposed between the first metal layer and a semiconductor body of the semiconductor die, wherein a thickness of the first metal layer is greater than a thickness of the second metal layer, and wherein the first metal layer has a different metal composition as the second metal layer.

A method of forming a semiconductor device includes providing a carrier comprising a die attach pad, providing a semiconductor die that includes a bond pad disposed on a main surface of the semiconductor die, and providing a metal interconnect element, arranging the semiconductor die on the die attach pad such that the bond pad faces away from the die attach pad, and welding the metal interconnect element to the bond pad, wherein the bond pad comprises first and second metal layers, wherein the second metal layer is disposed between the first metal layer and a semiconductor body of the semiconductor die, wherein a thickness of the first metal layer is greater than a thickness of the second metal layer, and wherein the first metal layer has a different metal composition as the second metal layer.

An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.

An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.

A power semiconductor device is proposed. The power semiconductor device includes a semiconductor substrate. The power semiconductor device further includes an electrically conducting first layer. At least part of the electrically conducting first layer includes pores. The power semiconductor device further includes an electrically conducting second layer. The electrically conducting second layer is arranged between the semiconductor substrate and the electrically conducting first layer. The pores are at least partially filled with a phase change material.

A power semiconductor device is proposed. The power semiconductor device includes a semiconductor substrate. The power semiconductor device further includes an electrically conducting first layer. At least part of the electrically conducting first layer includes pores. The power semiconductor device further includes an electrically conducting second layer. The electrically conducting second layer is arranged between the semiconductor substrate and the electrically conducting first layer. The pores are at least partially filled with a phase change material.

Embodiments relate to the design of a device capable of increasing the electrical performance of an interconnect feature by amplifying the current carrying capacity of an interconnect feature. The device comprises a first body comprising a first surface with at least one nanoporous conductive structure protruding from the first surface. The device further comprises a second body comprising a second surface with arrays of nanofibers extending from the second surface and penetrating into corresponding nanoporous conductive structures to form conductive pathways between the first body and the second body.

Embodiments relate to the design of a device capable of increasing the electrical performance of an interconnect feature by amplifying the current carrying capacity of an interconnect feature. The device comprises a first body comprising a first surface with at least one nanoporous conductive structure protruding from the first surface. The device further comprises a second body comprising a second surface with arrays of nanofibers extending from the second surface and penetrating into corresponding nanoporous conductive structures to form conductive pathways between the first body and the second body.

A semiconductor device includes: a substrate having an obverse and a reverse face; wirings on the obverse face such as a first and a second drive wiring; a semiconductor element connected to the first and second drive wirings; a first drive conductor on the same side as the semiconductor element with respect to the substrate outside of the semiconductor element as viewed in a thickness direction and connected to the first drive wiring; a second drive conductor on the same side as the semiconductor element with respect to the substrate outside of the semiconductor element as viewed in the thickness direction and connected to the second drive wiring; and a sealing resin covering the wirings and the semiconductor element, while also covering the first and second drive conductor such that their faces opposite to the substrate in the thickness direction are exposed. The first and the second drive conductor are separated in a direction parallel to the obverse face. The first drive conductor is smaller in volume than the second drive conductor.

According to various embodiments, a method for processing a substrate may include: processing a plurality of device regions in a substrate separated from each other by dicing regions, each device region including at least one electronic component; wherein processing each device region of the plurality of device regions includes: forming a recess into the substrate in the device region, wherein the recess is defined by recess sidewalls of the substrate, wherein the recess sidewalls are arranged in the device region; forming a contact pad in the recess to electrically connect the at least one electronic component, wherein the contact pad has a greater porosity than the recess sidewalls; and singulating the plurality of device regions from each other by dicing the substrate in the dicing region.