A package structure of a semiconductor device includes a first substrate, a second substrate, and a bonding layer. The bonding layer bonds the first substrate and the second substrate. The bonding layer includes an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer. The outer bonding pad pattern surrounds the inner bonding pad pattern. The outer bonding pad pattern includes first bonding pads, the inner bonding pad pattern includes second bonding pads, a density of the first bonding pads is greater than that of the second bonding pads. The first bonding pads of the outer bonding pad pattern is distributed to form a plurality of pad rings surrounding the inner bonding pad pattern, and the first bonding pads of the plurality of pad rings are aligned in a horizontal direction or a vertical direction.

A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads.

A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a bump and a first dummy bump between the chip and the substrate. The bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, and the first dummy bump is wider than the bump. The chip package structure includes a first dummy solder layer under the first dummy bump and having a curved bottom surface facing and spaced apart from the substrate.

A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors underlying and electrically coupled to the plurality of redistribution lines. The plurality of non-solder electrical connectors includes a corner electrical connector. The corner electrical connector is elongated. An electrical connector is farther away from the corner than the corner electrical connector, wherein the electrical connector is non-elongated.

A semiconductor device includes a semiconductor die having first and second conductive pads, and a substrate having third and fourth bonding pads. A width ratio of the first conductive pad over the third bonding pad at an inner region is different from a width ratio of the second conductive pad over the fourth bonding pad at an outer region.

The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed on a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top surface of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top surface layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the wafer substrate is exposed.

An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other.

A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.