A nonvolatile memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines extending in a first direction, bitlines extending in a second direction, and a memory cell array connected to the wordlines and the bitlines. The second semiconductor layer is beneath the first semiconductor layer in a third direction, and includes a substrate and an address decoder on the substrate. The address decoder controls the memory cell array, and includes pass transistors connected to the wordlines, and drivers control the pass transistors. In the second semiconductor layer, the drivers are arranged by a first layout pattern along the first and second directions, and the pass transistors are arranged by a second layout pattern along the first and second directions. The first layout pattern is different from the second layout pattern, and the first layout pattern is independent of the second layout pattern.

A method for assembling a first substrate and a second substrate by metal-metal direct bonding, includes providing a first layer of a metal at the surface of the first substrate and a second layer of the metal at the surface of the second substrate, the first and second metal layers having a tensile stress (.sub.i) between 30% and 100% of the tensile yield strength (.sub.e) of the metal; assembling the first and second substrates at a bonding interface by directly contacting the first and second tensile stressed metal layers; and subjecting the assembly of the first and second substrates to a stabilization annealing at a temperature lower than or equal to a temperature threshold beyond which the first and second tensile stressed metal layers are plastically compressively deformed.

A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.

A method for assembling a first substrate and a second substrate by metal-metal direct bonding, includes providing a first layer of a metal at the surface of the first substrate and a second layer of the metal at the surface of the second substrate, the first and second metal layers having a tensile stress (.sub.i) between 30% and 100% of the tensile yield strength (.sub.e) of the metal; assembling the first and second substrates at a bonding interface by directly contacting the first and second tensile stressed metal layers; and subjecting the assembly of the first and second substrates to a stabilization annealing at a temperature lower than or equal to a temperature threshold beyond which the first and second tensile stressed metal layers are plastically compressively deformed.

A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.

A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers.

A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.

The invention provides a semiconductor structure, which comprises a first chip and a second chip attached to each other, wherein the first chip comprises a quantum dot pattern, and the second chip comprises a through silicon via (TSV), wherein the quantum dot pattern and the through silicon via are aligned with each other.

A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers.

A substrate structure and a manufacturing method thereof are provided, in which a core layer having first and second connection pads is formed, and first bonding pads of a first circuit build-up layer and second bonding pads of a second circuit build-up layer are respectively bonded to the first connection pads and the second connection pads, so that the first circuit build-up layer and the second circuit build-up layer are respectively located on a first side and a second side of the core layer, and a first gap is formed between the first side and the first circuit build-up layer, and a second gap is formed between the second side and the second circuit build-up layer. Thereby, the core layer and the first and second circuit build-up layers can be manufactured separately and concurrently, thereby shortening the manufacturing process of the substrate structure and improving the yield of the substrate structure.