A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.

A multi-chip package structure includes outer leads, a first chip and a second chip. The outer leads are disposed on four sides of a chip bonding area of a package carrier thereof, respectively. The first chip is fixed on the chip bonding area and includes a core and a seal ring. Input/output units, and first bonding pads are disposed, in an outward order, on the sides of the core. Each first bonding pad is electrically connected to a corresponding outer lead through a first wire. Dummy pads are disposed between the input/output units and the at least one side of the core. The second chip is stacked on the core and includes second bonding pads connected to the corresponding outer leads through second wires and dummy pads, so as to prevent from short circuit caused by soldering overlap and contact between the wires.

A multi-chip package structure includes outer leads, a first chip and a second chip. The outer leads are disposed on a side of a chip bonding area of a package carrier thereof. The first chip is fixed on the chip bonding area and includes a core and a seal ring. Input/output units, and first bonding pads are disposed, in an outward order, on at a side of the core. Each first bonding pad is electrically connected to a corresponding outer lead through a first wire. Dummy pads are disposed between the input/output units and adjacent first bonding pads on the side of the core. The second chip is stacked on the core and includes second bonding pads connected to the corresponding outer leads through second wires and dummy pads, so as to prevent from short circuit caused by soldering overlap and contact between the wires.

A multi-chip package structure includes outer leads, a first chip and a second chip. The outer leads are disposed on four sides of a chip bonding area of a package carrier thereof, respectively. The first chip is fixed on the chip bonding area and includes a core and a seal ring. Input/output units, and first bonding pads are disposed, in an outward order, on the sides of the core. Each first bonding pad is electrically connected to a corresponding outer lead through a first wire. Dummy pads are disposed between the input/output units and the at least one side of the core. The second chip is stacked on the core and includes second bonding pads connected to the corresponding outer leads through second wires and dummy pads, so as to prevent from short circuit caused by soldering overlap and contact between the wires.

A multi-chip package structure includes outer leads, a first chip and a second chip. The outer leads are disposed on a side of a chip bonding area of a package carrier thereof. The first chip is fixed on the chip bonding area and includes a core and a seal ring. Input/output units, and first bonding pads are disposed, in an outward order, on at a side of the core. Each first bonding pad is electrically connected to a corresponding outer lead through a first wire. Dummy pads are disposed between the input/output units and adjacent first bonding pads on the side of the core. The second chip is stacked on the core and includes second bonding pads connected to the corresponding outer leads through second wires and dummy pads, so as to prevent from short circuit caused by soldering overlap and contact between the wires.

A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.

A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.

A semiconductor device has a substrate with a die mounting site and a plurality of leads. A first electrical component is disposed over a first surface of the die mounting site. A second electrical component is disposed over a second surface of the die mounting site opposite the first surface of the die mounting site. A first bond wire is coupled between the first electrical component and a first lead, and a second bond wire is coupled between the second electrical component and a second lead. A first encapsulant is deposited over the first electrical component, and a second encapsulant is deposited over the second electrical component with the leads exposed between the first encapsulant and second encapsulant. The leads are exposed from the first encapsulant and second encapsulant on a side of the semiconductor device.

A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.

A semiconductor package includes a buffer die, memory dies sequentially stacked on the buffer die, a bonding layer that extends between ones of the memory dies and configured to bond the memory dies with each other, and a molding member on the buffer die and covering or overlapping sidewalls of the memory dies. Each of the memory dies includes a substrate having first and second surfaces opposite to each other in a vertical direction substantially perpendicular to an upper surface of the buffer die, and a first signal pad and a test pad structure beneath the first surface of the substrate. The test pad structure includes a test pad and a first conductive pattern stacked in the vertical direction on the first surface of the substrate. The first conductive pattern has an uneven lower surface.