A semiconductor device includes a first die, a second die on the first die, and a third die on the second die, the second die being interposed between the first die and the third die. The first die includes a first substrate and a first interconnect structure on an active side of the first substrate. The second die includes a second substrate, a second interconnect structure on a backside of the second substrate, and a power distribution network (PDN) structure on the second interconnect structure such that the second interconnect structure is interposed between the PDN structure and the second substrate.

A method of manufacturing a bonded substrate stack includes: providing a first substrate having a first hybrid interface layer, the first hybrid interface layer including a first insulator and a first metal; and providing a second substrate having a second hybrid interface layer, the second hybrid interface layer including a second insulator and a second metal. The hybrid interface layers are surface-activated by particle bombardment which is configured to remove atoms of the first hybrid interface layer and atoms of the second hybrid interface layer to generate dangling bonds on the hybrid interface layers. The surface-activated hybrid interface layers are brought into contact, such that the dangling bonds of the first hybrid interface layer and the dangling bonds of the second hybrid interface layer bond together to form first insulator to second insulator bonds and first metal to second metal bonds.

A method includes forming a first substrate including a first dielectric layer and a first metal pad, forming a second substrate including a second dielectric layer and a second metal pad, and bonding the first dielectric layer to the second dielectric layer, and the first metal pad to the second metal pad. One or both of the first and second substrates is formed by forming a first insulating layer, forming an opening in the layer, forming a barrier on an inner surface of the opening, forming a metal pad material on the barrier, polishing the metal pad material to expose a portion of the barrier and to form a gap, expanding the gap, forming a second insulating layer to fill the opening and the gap, and polishing the insulating layers such that a top surface of the metal pad is substantially planar with an upper surface of the polished layer.

Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.

This method for producing a structure wherein base materials are bonded by atomic diffusion comprises: a step for applying a liquid resin on the base material; a step for smoothing the surface of the liquid resin by surface tension; a step for forming a resin layer by curing; a step for forming a metal thin film on the resin layer; a step for forming a metal thin film on the base material; and a step for bringing the metal thin film of the base material and the metal thin film of the base material into close contact with each other, thereby bonding the metal thin film of the resin layer and the metal thin film of the base material with each other by atomic diffusion.

A semiconductor package includes: a first semiconductor chip; a second semiconductor chip; and a bonding structure at an interface between the first and second semiconductor chips. The bonding structure includes: a first bonding insulating layer on the first semiconductor chip; a first connection pad in a first pad opening formed in the first bonding insulating layer, the first connection pad including a first pad layer, a first interface layer including a copper oxide, and a first capping layer; a second bonding insulating layer on the second semiconductor chip; and a second connection pad in a second pad opening formed in the second bonding insulating layer, the second connection pad including a second pad layer, a second interface layer including a copper oxide, and a second capping layer. The first and second capping layers include copper monocrystal layers having a (111) orientation.

A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads laterally surrounded by a first pad-level dielectric layer. The first pad-level dielectric layer includes at least one first encapsulated airgap located between neighboring pairs of first bonding pads and encapsulated by a first dielectric fill material of the first pad-level dielectric layer. The bonded assembly includes a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads laterally surrounded by a second pad-level dielectric layer. Each of the second bonding pads is bonded to a respective one of the first bonding pads.

Disclosed are semiconductor packages and their fabricating methods. A semiconductor package includes a semiconductor chip on a redistribution substrate. The redistribution substrate includes a base dielectric layer and upper coupling pads in the base dielectric layer. Top surfaces of the upper coupling pads are coplanar with a top surface of the base dielectric layer. The semiconductor chip includes a redistribution dielectric layer and redistribution chip pads in the redistribution dielectric layer. Top surfaces of the redistribution chip pads are coplanar with a top surface of the redistribution dielectric layer. The top surface of the redistribution dielectric layer is bonded to the top surface of the base dielectric layer. The redistribution chip pads are bonded to the upper coupling pads. The redistribution chip pads and the upper coupling pads include a same metallic material. The redistribution dielectric layer and the base dielectric layer include a photosensitive polymer layer.

Disclosed are semiconductor packages and their fabricating methods. A semiconductor package includes a semiconductor chip on a redistribution substrate. The redistribution substrate includes a base dielectric layer and upper coupling pads in the base dielectric layer. Top surfaces of the upper coupling pads are coplanar with a top surface of the base dielectric layer. The semiconductor chip includes a redistribution dielectric layer and redistribution chip pads in the redistribution dielectric layer. Top surfaces of the redistribution chip pads are coplanar with a top surface of the redistribution dielectric layer. The top surface of the redistribution dielectric layer is bonded to the top surface of the base dielectric layer. The redistribution chip pads are bonded to the upper coupling pads. The redistribution chip pads and the upper coupling pads include a same metallic material. The redistribution dielectric layer and the base dielectric layer include a photosensitive polymer layer.

A memory device is disclosed. The disclosed memory device may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a column control circuit. The second wafer may include a second logic structure including a row control circuit.