There is provided a solid-state imaging device capable of reducing the number of wiring layers and achieving downsizing with flexible layout designing. The solid-state imaging device includes a first semiconductor chip including a first electrode pad, first wiring connected to a first electrode pad through a first via, and a logic circuit, which are formed therein, and a second semiconductor chip connected to the first semiconductor chip and including a second electrode pad, second wiring connected to the second electrode pad through a second via, and a pixel array, which are formed therein. The first electrode pad and the second electrode pad are bonded as being shifted from each other on a bonding surface of the first semiconductor chip and the second semiconductor chip. A total length of the shifted and bonded first and second electrode pads in an extending-direction of the wiring having a longer pitch of the first and second wiring is twice or more of an extending-direction length of the wiring having the longer pith.

An aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method includes preparing a lead frame. The lead frame includes a first lead including a pad and a first terminal. The pad includes a pad main surface and a pad back surface that face opposite sides to each other in a first direction. The first terminal extends from the pad along a second direction that is perpendicular to the first direction. The method includes: preparing a first semiconductor element and a second semiconductor element, each of the first semiconductor element and the second semiconductor element having an element main surface and an element back surface that face opposite sides to each other; die bonding the element back surface of the first semiconductor element to the pad main surface by using a first solder; and die bonding the element back surface of the second semiconductor element to the pad main surface by using a second solder having a melting point lower than a melting point of the first solder, after die bonding the element back surface of the first semiconductor element to the pad main surface by using the first solder.

An aspect of the present disclosure provides a method of manufacturing a semiconductor device. The method includes: preparing a first semiconductor element and a second semiconductor element, each of the first semiconductor element and the second semiconductor element having an element main surface and an element back surface that face opposite sides to each other; die bonding the element back surface of the first semiconductor element to a pad main surface by using a first solder; and die bonding the element back surface of the second semiconductor element to the pad main surface by using a second solder having a melting point lower than a melting point of the first solder, after die bonding the element back surface of the first semiconductor element to the pad main surface by using the first solder.

An electronics package includes an interconnect assembly comprising a first insulating substrate, a first wiring layer formed on a lower surface of the first insulating substrate, and at least one through hole extending through the first insulating substrate and the first wiring layer. The electronics package also includes an electrical component assembly comprising an electrical component having an active surface coupled to an upper surface of the first insulating substrate opposite the lower surface. The active surface of the electrical comprises at least one metallic contact pad. At least one conductive stud is coupled to the at least one metallic contact pad and is positioned within the at least one through hole. A conductive plug contacts the first wiring layer and extends into the at least one through hole to at least partially surround the at least one conductive stud.

There is provided a solid-state imaging device capable of reducing the number of wiring layers and achieving downsizing with flexible layout designing. The solid-state imaging device includes a first semiconductor chip including a first electrode pad, first wiring connected to a first electrode pad through a first via, and a logic circuit, which are formed therein, and a second semiconductor chip connected to the first semiconductor chip and including a second electrode pad, second wiring connected to the second electrode pad through a second via, and a pixel array, which are formed therein. The first electrode pad and the second electrode pad are bonded as being shifted from each other on a bonding surface of the first semiconductor chip and the second semiconductor chip. A total length of the shifted and bonded first and second electrode pads in an extending-direction of the wiring having a longer pitch of the first and second wiring is twice or more of an extending-direction length of the wiring having the longer pith.

A semiconductor device is provided. The semiconductor includes a supporting silicon layer and a memory module. The memory module and the supporting silicon layer are bonded via a bonding structure. The bonding structure includes at least one bonding film whose thickness is less than 200 ?.

The present disclosure relates to a method for forming a semiconductor device structure. The method includes forming a first semiconductor die and forming a second semiconductor die. The first semiconductor die includes a first metal layer, a first conductive via over the first metal layer, and a first conductive polymer liner surrounding the first conductive via. The second semiconductor die includes a second metal layer, a second conductive via over the second metal layer, and a second conductive polymer liner surrounding the second conductive via. The method also includes forming a conductive structure electrically connecting the first metal layer and the second metal layer by bonding the second semiconductor die to the first semiconductor die. The conductive structure is formed by the first conductive via, the first conductive polymer liner, the second conductive via, and the second conductive polymer liner.

The invention provides a bond wire arrangement comprising a signal bond wire (1) for operably connecting a first electronic device (6) to a second electronic device (8), and a control bond wire (2) being arranged alongside the signal bond wire at a distance so as to have a magnetic coupling with the signal bond wire (1), and having a first end (11) coupled to ground, and a second end (12) coupled to ground via a resistive element (14). The proposed solution allows the control of the Q factor (losses) of wire bond inductors during assembly phase, which will save time and reduce overall design cycle as compared to known methods.

An electronics package includes an interconnect assembly comprising a first insulating substrate, a first wiring layer formed on a lower surface of the first insulating substrate, and at least one through hole extending through the first insulating substrate and the first wiring layer. The electronics package also includes an electrical component assembly comprising an electrical component having an active surface coupled to an upper surface of the first insulating substrate opposite the lower surface. The active surface of the electrical comprises at least one metallic contact pad. At least one conductive stud is coupled to the at least one metallic contact pad and is positioned within the at least one through hole. A conductive plug contacts the first wiring layer and extends into the at least one through hole to at least partially surround the at least one conductive stud.

An electronics package includes an interconnect assembly comprising a first insulating substrate, a first wiring layer formed on a lower surface of the first insulating substrate, and at least one through hole extending through the first insulating substrate and the first wiring layer. The electronics package also includes an electrical component assembly comprising an electrical component having an active surface coupled to an upper surface of the first insulating substrate opposite the lower surface. The active surface of the electrical comprises at least one metallic contact pad. At least one conductive stud is coupled to the at least one metallic contact pad and is positioned within the at least one through hole. A conductive plug contacts the first wiring layer and extends into the at least one through hole to at least partially surround the at least one conductive stud.