An encapsulation of laser direct structuring (LDS) material is molded onto first and second semiconductor dice. A die-to-die coupling formation between the first and second semiconductor dice includes die vias extending through the LDS material to reach the first and second semiconductor dice and a die-to-die line extending at a surface of the encapsulation between the die vias. After laser activating and structuring selected locations of the surface of the encapsulation for the die vias and die-to-die line, the locations are placed into contact with an electrode that provides an electrically conductive path. Metal material is electrolytically grown onto the locations of the encapsulation by exposure to an electrolyte carrying metal cations. The metal cations are reduced to metal material via a current flowing through the electrically conductive path provided via the electrode. The electrode is then disengaged from contact with the locations having metal material electrolytically grown thereon.

An encapsulation of laser direct structuring (LDS) material is molded onto a substrate having first and second semiconductor dice arranged thereon. Laser beam energy is applied to a surface of the encapsulation of LDS material to structure therein die vias extending through the LDS material to the first and second semiconductor dice and a die-to-die line extending at surface of the LDS material between die vias. Laser-induced forward transfer (LIFT) processing is applied to transfer electrically conductive material to the die vias and the die-to-die line extending between die vias. A layer of electrically conductive material electroless grown onto the die vias and the die-to-die line facilitates improved adhesion of the electrically conductive material transferred via LIFT processing.

The present disclosure provides a chip packaging method and a package structure. The chip packaging method comprises: forming a wafer conductive layer on a wafer active surface of a wafer; forming a protective layer having certain material properties on the wafer conductive layer, the protective layer encapsulating the wafer conductive layer and exposing a front surface of the wafer conductive layer; separating (such as cutting) the wafer formed with the wafer conductive layer and the protective layer to form a die; attaching (such as adhering) the die onto a carrier; forming a molding layer having certain material properties on a die back surface of the die on the carrier; removing (such as stripping off) the carrier; forming a panel-level conductive layer electrically connected with the wafer conductive layer; and forming a dielectric layer. The package structure has a series of structural and material properties, so as to reduce warpage in the packaging process, lower a requirement on an accuracy of aligning the die, reduce a difficulty in the packaging process, and make the packaged chip more durable, and thus the present disclosure is especially suitable for large panel-level package and package of a thin chip with a large electric flux.

A multichip module comprises a carrier, a plurality of chips, an electrical insulating layer, and an electrical interconnect structure. The carrier includes a bottom wall and four side walls defining an internal cavity. The chips are positioned in the internal cavity, with each chip including a plurality of bond pads. The electrical insulating layer is formed from electrically insulating material and is positioned on an upper surface of the carrier and the chips. The electrical interconnect structure includes a plurality of interconnect traces, with each interconnect trace formed from electrically conductive material and electrically connected to a first bond pad on a first chip and a second bond pad on a second chip. Each interconnect trace includes a bridge having a segment that is spaced apart from, and positioned above, the electrical insulating layer.

A method for manufacturing a semiconductor device provided with a semiconductor chip includes: disposing the semiconductor chip such that an electrode of the semiconductor chip is abutted against a peeling portion provided on a substrate; forming an anchor portion, which defines a position of the semiconductor chip and has flexibility so as to be freely bendable, such that the anchor portion covers the peeling portion and the semiconductor chip; forming a sealing portion that is abutted against the anchor portion and has flexibility so as to be freely bendable; and separating the peeling portion and the substrate from the semiconductor chip and the anchor portion and exposing the electrode of the semiconductor chip. The anchor portion is formed by at least one of a vapor phase deposition method, a spray coating method, and an inkjet method.

A package structure including IPD and method of forming the same are provided. The package structure includes a die, an encapsulant laterally encapsulating the die, a first RDL structure disposed on the encapsulant and the die, an IPD disposed on the first RDL structure and an underfill layer. The IPD includes a substrate, a first connector on a first side of the substrate and electrically connected to the first RDL structure, a guard structure on a second side of the substrate opposite to the first side and laterally surrounding a connector region, and a second connector disposed within the connector region and electrically connected to a conductive via embedded in the substrate. The underfill layer is disposed to at least fill a space between the first side of the IPD and the first RDL structure. The underfill layer is separated from the connector region by the guard structure.

A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a wiring structure and an interposer via electrically connected to the wiring structure; a plurality of semiconductor chips located on a first surface of the interposer and electrically connected to each other through the interposer; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface, wherein the plurality of semiconductor chips are electrically connected to the redistribution circuit structure through at least the interposer.

A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

A semiconductor device may include a semiconductor chip in an encapsulant. A first insulation layer may be disposed on the encapsulant and the semiconductor chip. A horizontal wiring and a primary pad may be disposed on the first insulation layer. A secondary pad may be disposed on the primary pad. A second insulation layer covering the horizontal wiring may be disposed on the first insulation layer. A solder ball may be disposed on the primary pad and the secondary pad. The primary pad may have substantially the same thickness as a thickness of the horizontal wiring.

A preparation method of a thin power device comprising the steps of steps S1, S2 and S3. In step S1, a substrate is provided. The substrate comprises a first set of first contact pads and a second set of second contact pads arranged at a front surface and a back surface of the substrate respectively. Each first contact pad of the first set of contact pads is electrically connected with a respective second contact pad of the second set of contact pads via a respective interconnecting structure formed inside the substrate. A through opening is formed in the substrate aligning with a third contact pad attached to the back surface of the substrate. The third contact pad is not electrically connected with the first set of contact pads. In step S2, a semiconductor chip is embedded into the through opening. A back metal layer at a back surface of the semiconductor chip is attached to the third contact pad. In step S3, a respective electrode of a plurality of electrodes at a front surface of the semiconductor chip is electrically connected with said each first contact pad of the first set of contact pads via a respective conductive structure of a plurality of conductive structures.