An electronic circuit device according to the present invention includes a base substrate including a wiring layer having a connection part, at least one electronic circuit element, and a re-distribution layer including a photosensitive resin layer, the photosensitive resin layer enclosing a surface on which a connection part of the electronic circuit element is formed and a side surface of the electronic circuit element and embedding a first wiring photo via, a second wiring photo via and a wiring, the first wiring photo via directly connected to the connection part of the electronic circuit element, the second wiring photo via arranged at the outer periphery of the electronic circuit element and directly connected to a connection part of the wiring layer, the wiring electrically connected to the first wiring photo via and the second wiring photo via on a same surface.

A display device includes a substrate including a display area in which pixels are located, and a non-display area, first and second electrodes in the display area and spaced from each other, light emitting elements between the first and second electrodes, connection electrodes electrically connected to the light emitting elements, a fan-out line electrically connected to the pixels in the non-display area, a first pad electrode on the fan-out line, a pad connection electrode on the fan-out line and the first pad electrode, and electrically connecting the fan-out line and the first pad electrode, and a second pad electrode at a same layer as at least one of the connection electrodes, and contacting the first pad electrode.

An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.

A display device includes: a substrate; a plurality of pixel columns on the substrate, each of the plurality of pixel columns including a plurality of pixel groups each including a first pixel and a second pixel arranged along a first direction; and a bank enclosing a perimeter of each of the plurality of pixel groups, the bank including a first opening corresponding to each of the plurality of pixel groups, and a second opening located between two pixel groups adjacent to each other in the first direction among the plurality of pixel groups.

A display device includes pixels, each of the pixels including light emitting elements disposed in pixels, a color conversion layer disposed on the light emitting elements of the pixels, an optical layer disposed on the color conversion layer, and an organic layer disposed on the optical layer. At least one of the optical layer and the organic layer includes recess patterns disposed between the pixels.

A display device includes a conductive pattern on a substrate, a via layer on the conductive pattern with a via hole exposing the conductive pattern, a first electrode and a second electrode on the via layer and spaced apart from each other, a first insulating layer on the first electrode and the second electrode, a bank layer on the first insulating layer defining an emission area and a subarea, a light-emitting element on the first insulating layer, and a first connection electrode and a second connection electrode on the first insulating layer and the light-emitting element. The first connection electrode electrically contacts an end of the light-emitting element, and the second connection electrode electrically contacts another end of the light-emitting element. The bank layer includes a bank extension portion extended to the subarea and the bank extension portion overlaps at least a portion of the via hole.

A system and method of providing high bandwidth and low latency memory architecture solutions for next generation processors is disclosed. The package contains a substrate, a memory device embedded in the substrate via EMIB processes and a processor disposed on the substrate partially over the embedded memory device. The I/O pads of the processor and memory device are vertically aligned to minimize the distance therebetween and electrically connected through EMIB uvias. An additional memory device is disposed on the substrate partially over the embedded memory device or on the processor. I/O signals are routed using a redistribution layer on the embedded memory device or an organic VHD redistribution layer formed over the embedded memory device when the additional memory device is laterally adjacent to the processor and the I/O pads of the processor and additional memory device are vertically aligned when the additional memory device is on the processor.

The present disclosure provides a method for fabricating a semiconductor device including performing a bonding process to bond a second die onto a first die, forming a first mask layer on the second die, forming a first opening along the first mask layer and the second die, and extending to the first die, forming isolation layers on sidewalls of the first opening, forming protection layers covering upper portions of the isolation layers, and forming a conductive filler layer in the first opening.

A display device includes a display area comprising pixels, a fan-out area, a pad area, a display driver, a metal layer disposed on a substrate, a data line, a first voltage line, and a second voltage line extending in a first direction on the metal layer in the display area, a fan-out line electrically connecting the data line to the display driver on the metal layer in the fan-out area, a gate line disposed on the metal layer in the display area and extending in a second direction intersecting the first direction, a source-drain layer disposed on the gate line, and an electrode layer disposed on the source-drain layer. The first voltage line includes a first plate portion disposed on the source-drain layer in the fan-out area, and the second voltage line comprises a second plate portion disposed on the electrode layer in the fan-out area.

A semiconductor package includes a lower semiconductor device, a plurality of conductive pillars, an upper semiconductor device, an encapsulating material, and a redistribution structure. The plurality of conductive pillars are disposed on the lower semiconductor device along a direction parallel to a side of the lower semiconductor device. The upper semiconductor device is disposed on the lower semiconductor device and reveals a portion of the lower semiconductor device where the plurality of conductive pillars are disposed, wherein the plurality of conductive pillars disposed by the same side of the upper semiconductor device and the upper semiconductor device comprises a cantilever part cantilevered over the at least one lower semiconductor device. The encapsulating material encapsulates the lower semiconductor device, the plurality of conductive pillars, and the upper semiconductor device. The redistribution structure is disposed over the upper semiconductor device and the encapsulating material.