A method comprises molding laser direct structuring material onto at least one semiconductor die, forming resist material on the laser direct structuring material, producing mutually aligned patterns of electrically-conductive formations in the laser direct structuring material and etched-out portions of the resist material having lateral walls sidewise of said electrically-conductive formations via laser beam energy, and forming electrically-conductive material at said etched-out portions of the resist material, the electrically-conductive material having lateral confinement surfaces at said lateral walls of said etched-out portions of the resist material.

A semiconductor package includes a semiconductor die, a first thermal conductive pattern and a second thermal conductive pattern. The semiconductor die is encapsulated by an encapsulant. The first thermal conductive pattern is disposed aside the semiconductor die in the encapsulant. The second thermal conductive pattern is disposed over the semiconductor die, wherein the first thermal conductive pattern is thermally coupled to the semiconductor die through the second thermal conductive pattern and electrically insulated from the semiconductor die.

This application discloses a package structure and a package system. The package structure may be used for packaging various types of chips, and is coupled to a PCB, so as to form the package system. The package structure includes a package base layer, a chip, a package body, and a connecting assembly. The package base layer has a first surface and a second surface that are opposite to each other. The chip is coupled to the first surface, and there is a chip pad on a surface that is of the chip and that is away from the package base layer. The package body covers the package base layer and the chip to protect the structure, and the chip pad is wired to a surface of the package body through the connecting assembly.

A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.

The present disclosure relates to an embedded packaging module comprising a first semiconductor device, a first packaging layer and a first wiring layer, the first semiconductor device having a first and a second face, at least two positioning bulges and at least one bonding pad being provided on the first face of the first semiconductor device; the first packaging layer being formed on both the first face and a surface adjacent to the first face, the positioning bulges being positioned in the first packaging layer, at least one first via hole being provided in the first packaging layer, the bottom of the first via hole being positioned in the bonding pad and contacting with the bonding pad; the first wiring layer being positioned on the side of the first packaging layer away from the first semiconductor device and being electrically connected with the bonding pad through the first via hole.

A method of forming a redistribution structure includes providing a dielectric layer. The dielectric layer is patterned to form a plurality of via openings. A seed layer is formed on the dielectric layer and filling in the plurality of via openings. A patterned conductive layer is formed a on the seed layer, wherein a portion of the seed layer is exposed by the patterned conductive layer. The portion of the seed layer is removed by using an etching solution, thereby forming a plurality of conductive lines and a plurality of vias. During the removing the portion of the seed layer, an etch rate of the patterned conductive layer is less than an etch rate of the seed layer.

An electronic device package includes an encapsulated electronic component, a substrate, a conductor and a buffer layer. The encapsulated electronic component includes a redistribution layer (RDL) and an encapsulation layer. The first surface is closer to the RDL than the second surface is. The encapsulation layer includes a first surface, and a second surface opposite to the first surface. The substrate is disposed on the second surface of the encapsulation layer. The conductor is disposed between the substrate and the encapsulated electronic component, and electrically connecting the substrate to the encapsulated electronic component. The buffer layer is disposed between the substrate and the encapsulated electronic component and around the conductor.

A semiconductor device, such as a QFN (Quad-Flat No-lead) package, includes an insulating encapsulation of a semiconductor chip. The insulating encapsulation is formed by a first encapsulation material which encapsulates the semiconductor chip and a second encapsulation material that is molded onto an upper surface of the first encapsulation material. The first encapsulation material includes an oblique cavity extending from the upper surface. The second encapsulation material includes an anchoring protrusion that enters into the cavity.

Semiconductor packages and methods for manufacturing are disclosed. In one example, a method for manufacturing a semiconductor package includes providing an electrically conductive chip carrier including a mounting surface and a protrusion extending out of the mounting surface. At least one semiconductor chip is arranged on the mounting surface. The method further includes encapsulating the protrusion and the at least one semiconductor chip in an encapsulation material, wherein surfaces of the protrusion and the at least one semiconductor chip facing away from the mounting surface remain uncovered by the encapsulation material. An electrical redistribution layer is formed over the surfaces of the protrusion and the at least one semiconductor chip facing away from the mounting surface. The electrical redistribution layer provides an electrical connection between the protrusion and the at least one semiconductor chip.

A semiconductor package structure includes a conductive pad formed over a substrate. The structure also includes a passivation layer formed over the conductive pad. The structure also includes a first via structure formed through the passivation layer and in contact with the conductive pad. The structure also includes a first encapsulating material surrounding the first via structure. The structure also includes a redistribution layer structure formed over the first via structure. The first via structure has a lateral extending portion embedded in the first encapsulating material near a top surface of the first via structure.