A package that includes a first integrated device comprising a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device comprising a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device through the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device.

A transparent display panel, a method for manufacturing the same, and a transparent display device are provided. the transparent display panel includes a first display substrate including: a first substrate and first pixel units thereon; and a second display substrate including: a second substrate and second pixel units thereon, the second pixel units are in one-to-one correspondence with the first pixel units, each first pixel unit includes a first display unit and a first transparent unit, and each second pixel unit includes a second display unit and a second transparent unit, an orthographic projection of the first display unit on the second substrate substantially coincides with that of the corresponding second display unit on the second substrate, and an orthographic projection of the first transparent unit on the second substrate substantially coincides with that of the corresponding second transparent unit on the second substrate.

The present disclosure provides a method for preparing a semiconductor device with a composite dielectric structure. The method includes forming a photoresist pattern structure over a first semiconductor die. The method also includes forming a second dielectric layer surrounding the photoresist pattern structure, and removing the photoresist pattern structure to form a first opening in the second dielectric layer. The method further includes forming dielectric spacers along sidewalls of the first opening, and forming an interconnect structure surrounded by the dielectric spacers. In addition, the method includes bonding a second semiconductor die to the second dielectric layer. The second semiconductor die includes a second conductive pad facing the interconnect structure, and the second conductive pad is electrically connected to the first conductive pad of the first semiconductor die through the interconnect structure.

A heat dissipation structure of an electric component that generates heat includes: a heat dissipator provided along a surface of the electric component; a liquid metal interposed between the electric component and the heat dissipator; and a fencing body interposed between the electric component and the heat dissipator in a crushed state and surrounding the liquid metal.

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

A semiconductor package includes a first semiconductor chip having a first surface and a second surface. First connection pads are adjacent to the first surface. A second semiconductor chip has a lower surface facing the first surface of the first semiconductor chip and includes second connection pads, Connection bumps contact the first connection pads and the second connection pads between the first semiconductor chip and the second semiconductor chip. An adhesive layer is interposed between the first semiconductor chip and the second semiconductor chip to at least partially surround the connection bumps. The adhesive layer includes a protruding portion protruding from a side surface of the second semiconductor chip. A barrier structure covers a portion of the first connection pads, partially overlapping the second semiconductor chip on the first surface, and contacting the protruding portion of the adhesive layer.

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a bump and a first dummy bump between the chip and the substrate. The bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, and the first dummy bump is wider than the bump. The chip package structure includes a first dummy solder layer under the first dummy bump and having a curved bottom surface facing and spaced apart from the substrate.

A semiconductor device includes an interconnect structure disposed over a first semiconductor die. The first semiconductor die includes a semiconductor substrate and a first conductive pad disposed over the semiconductor substrate, and the first conductive pad is covered by the interconnect structure. The semiconductor device also includes dielectric spacers surrounding the interconnect structure. An interface between the dielectric spacers and the interconnect structure is curved. The semiconductor device further includes a dielectric layer surrounding the dielectric spacers, and a second semiconductor die bonded to the dielectric layer and the interconnect structure. The second semiconductor die includes a second conductive pad, and the interconnect structure is covered by the second conductive pad.

Methods and compositions are described for controlling bond line thickness of a joint formed during sintering. Spacer particles of a predetermined particle type and size are added in a predetermined concentration to a sintering paste to form a sintering paste mixture prior to sintering to achieve a targeted bond line thickness during sintering. The sintering paste mixture can be sintered under pressure and pressure-less process conditions. Under pressured sintering, the amount of pressure applied during sintering may be adjusted depending on the composition and concentration of the spacer particles to adjust bond line thickness.

In order to prevent cracks from occurring at the corners of semiconductor dies after the semiconductor dies have been bonded to other substrates, an opening is formed adjacent to the corners of the semiconductor dies, and the openings are filled and overfilled with a buffer material that has physical properties that are between the physical properties of the semiconductor die and an underfill material that is placed adjacent to the buffer material.