Methods for reducing the junction temperature between an IC chip and its lid by including metal spacers in the TIM layer and the resulting devices are disclosed. Embodiments include providing a substrate, including integrated circuit devices, having front and back sides; forming vertical spacers on the backside of the substrate; providing a plate parallel to and spaced from the backside of the substrate; and forming a TIM layer, surrounding the vertical spacers, between the backside of the substrate and the plate.

A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS.

A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS.

A power chip package structure and a manufacturing method thereof are disclosed. The power chip package structure includes a carrier, a self-correction layer, a conductive paste, and a power chip. The carrier includes a ceramic board and an inner metal layer that is formed on the ceramic board and that has a connection pad. The self-correction layer is formed on the inner metal layer, and the self-correction layer and the connection pad jointly define a slot. The self-correction layer includes a glue body and a plurality of elastic spacers covered by the glue body. The conductive paste is filled into the slot. The power chip includes a chip body disposed on the self-correction layer and a bonding pad that is formed on the chip body. The bonding pad is connected to the conductive paste, such that the power chip is electrically coupled to the carrier.