A power semiconductor component is specified, having a power semiconductor device arranged within a housing, wherein a heat sink is exposed on a first surface of the housing; a wiring substrate which receives the housing with the power semiconductor device and which has a first main surface and a second main surface. A heat dissipation region with increased thermal conductivity is arranged on the second main surface. The housing is arranged on the wiring substrate in such a way that the heat sink is connected to the heat dissipation region via a solder layer. A number of spacers which are arranged between the heat sink and the heat dissipation region are embedded in the solder layer. Furthermore, a method for producing a power semiconductor component is specified.

A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a die and a first adhesive layer; a surface of the substrate is provided with an insulation layer; the die is arranged on a surface of the insulation layer via the first adhesive layer; the insulation layer is provided with at least one hole slot; a position of the at least one hole slot corresponds to at least a part of an edge of the first adhesive layer; a second adhesive layer is arranged in the at least one hole slot; at least a part of a surface of the second adhesive layer is connected with the first adhesive layer; and an elasticity modulus of the second adhesive layer is smaller than an elasticity modulus of the first adhesive layer.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a die and a first adhesive layer; a surface of the substrate is provided with an insulation layer; the die is arranged on a surface of the insulation layer via the first adhesive layer; the insulation layer is provided with at least one slot; a position of the at least one slot corresponds to at least a part of an edge of the first adhesive layer; a second adhesive layer is arranged in the at least one slot; at least a part of a surface of the second adhesive layer is connected with the first adhesive layer; and an elasticity modulus of the second adhesive layer is smaller than an elasticity modulus of the first adhesive layer.

A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS.

A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS.

A power semiconductor component is specified, having a power semiconductor device arranged within a housing, wherein a heat sink is exposed on a first surface of the housing; a wiring substrate which receives the housing with the power semiconductor device and which has a first main surface and a second main surface. A heat dissipation region with increased thermal conductivity is arranged on the second main surface. The housing is arranged on the wiring substrate in such a way that the heat sink is connected to the heat dissipation region via a solder layer. A number of spacers which are arranged between the heat sink and the heat dissipation region are embedded in the solder layer. Furthermore, a method for producing a power semiconductor component is specified.

A wafer bonding method includes providing a first wafer including a first wafer surface, forming a first metal layer on the first wafer surface, and forming a first annular retaining wall structure including a first annular retaining wall and a second annular retaining wall surrounded by the first annular retaining wall. The first metal layer is formed between the first annular retaining wall and the second annular retaining wall. The method includes providing a second wafer including a second wafer surface, forming a second metal layer on the second wafer surface, and forming a second annular retaining wall structure including a third annular retaining wall and a fourth annular retaining wall surrounded by the third annular retaining wall. The second metal layer is formed between the third annular retaining wall and the fourth annular retaining wall. The method further includes bonding the first metal layer to the second metal layer.

Methods for reducing the junction temperature between an IC chip and its lid by including metal spacers in the TIM layer and the resulting devices are disclosed. Embodiments include providing a substrate, including integrated circuit devices, having front and back sides; forming vertical spacers on the backside of the substrate; providing a plate parallel to and spaced from the backside of the substrate; and forming a TIM layer, surrounding the vertical spacers, between the backside of the substrate and the plate.

A wafer bonding method includes providing a first wafer including a first wafer surface, forming a first metal layer on the first wafer surface, and forming a first annular retaining wall structure including a first annular retaining wall and a second annular retaining wall surrounded by the first annular retaining wall. The first metal layer is formed between the first annular retaining wall and the second annular retaining wall. The method includes providing a second wafer including a second wafer surface, forming a second metal layer on the second wafer surface, and forming a second annular retaining wall structure including a third annular retaining wall and a fourth annular retaining wall surrounded by the third annular retaining wall. The second metal layer is formed between the third annular retaining wall and the fourth annular retaining wall. The method further includes bonding the first metal layer to the second metal layer.