Patent classifications
H01L2224/2712
LAYERED BONDING MATERIAL, SEMICONDUCTOR PACKAGE, AND POWER MODULE
In a layered bonding material 10, a coefficient of linear expansion of a base material 11 is 5.5 to 15.5 ppm/K and a first surface and a second surface of the base material 11 are coated with pieces of lead-free solder 12a and 12b.
Terminal member made of plurality of metal layers between two heat sinks
A semiconductor device includes a semiconductor chip made of a SiC substrate and having main electrodes on one surface and a rear surface, first and second heat sinks, respectively, disposed adjacent to the one surface and the rear surface, a terminal member interposed between the second heat sink and the semiconductor chip, and a plurality of bonding members disposed between the main electrodes, the first and second heat sinks, and the terminal member. The terminal member includes plural types of metal layers symmetrically layered in the plate thickness direction. The terminal member as a whole has a coefficient of linear expansion at least in a direction orthogonal to the plate thickness direction in a range larger than that of the semiconductor chip and smaller than that of the second heat sink.
DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
A display device includes a substrate including a display area and a pad area, a plurality of pad electrodes disposed in the pad area on the substrate, a circuit board disposed to overlap at least a portion of the pad area on the substrate, and an anisotropic conductive layer disposed in the pad area between the substrate and the circuit board. The circuit board includes a base substrate and a plurality of bump electrodes disposed on a lower surface of the base substrate. The anisotropic conductive layer includes an adhesive layer and a plurality of conductive particles arranged in the adhesive layer. Each of the conductive particles includes a core, a first conductive film disposed on the core in a way such that at least a portion of the core is exposed, and a second conductive film entirely covering the core and the first conductive film.
Method for manufacturing semiconductor package
The present disclosure relates to a method for manufacturing a semiconductor package including vacuum-laminating a non-conductive film on a substrate on which a plurality of through silicon vias are provided and bump electrodes are formed, and then performing UV irradiation, wherein an increase in melt viscosity before and after UV irradiation can be adjusted to 30% or less, whereby a bonding can be performed without voids during thermo-compression bonding, and resin-insertion phenomenon between solders can be prevented, fillets can be minimized and reliability can be improved.
JOINING MATERIAL, PRODUCTION METHOD FOR JOINING MATERIAL, AND JOINED BODY
In the joined body (10) in which the conductor (12) and the substrate (14) are joined by the joining material (13), the joining material (13) includes a sintered body formed by sintering silver powder. A sintered body having a porosity of 8% to 30% and a surface roughness Ra of a joining surface of 500 nm or more and 3.3 μm or less is adopted.
ENGINEERED MATERIALS FOR ELECTRONICS ASSEMBLY
A solder material for use in electronic assembly, the solder material comprising: solder layers; and a core layer comprising a core material, the core layer being sandwiched between the solder layers, wherein: the thermal conductivity of the core material is greater than the thermal conductivity of the solder.
ENGINEERED MATERIALS FOR ELECTRONICS ASSEMBLY
A solder material for use in electronic assembly, the solder material comprising: solder layers; and a core layer comprising a core material, the core layer being sandwiched between the solder layers, wherein: the thermal conductivity of the core material is greater than the thermal conductivity of the solder.
Semiconductor device and manufacturing method for the semiconductor device
A semiconductor device includes first and second semiconductor elements and first and second conductive members. A first electrode on the first semiconductor element is bonded to a first stack part of the first conductive member by a first bonding layer. A second electrode on the second semiconductor element is bonded to a second stack part of the second conductive member by a second bonding layer. A first joint part of the first conductive member is bonded to a second joint part of the second conductive member by an intermediate bonding layer. A first surface of the first joint part facing the second joint part, a side surface of the first joint part continuous from the first surface, a second surface of the second joint part facing the first joint part, and a side surface of the second joint part continuous from the second surface are covered by nickel layers.
Method for transferring and bonding of devices
Provided is a method for transferring and bonding devices. The method includes applying an adhesive layer to a carrier, arranging a plurality of devices, attaching the arranged devices to the carrier, applying a polymer film to a substrate, aligning the carrier to which the plurality of devices are attached with the substrate, bonding the plurality of devices to the substrate by radiating laser, and releasing the carrier from the substrate to which the plurality of devices are bonded.
BONDING STRUCTURE, BONDING MATERIAL AND BONDING METHOD
A bonding structure bonds a Cu wiring line and a device electrode with each other. The bonding structure is arranged between the Cu wiring line and the device electrode, and comprises a first intermetallic compound (IMC) layer (a layer of an intermetallic compound of Cu and Sn) formed on the interface with the Cu wiring line, a second intermetallic compound (IMC) layer (a layer of an intermetallic compound of Cu and Sn) formed on the interface with the device electrode, and an intermediate layer that is present between the intermetallic compound layers. In the intermediate layer, a network-like IMC (a network-like intermetallic compound of Cu and Sn) is present in Sn.