A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

An anisotropic conductive film that can be produced in high productivity and can reduce a short circuit occurrence ratio has a first conductive particle layer in which conductive particles are dispersed at a predetermined depth in a film thickness direction, and a second conductive particle layer in which conductive particles are dispersed at a depth different from that in the first conductive particle layer. In the respective conductive particle layers, the closest distances between the adjacent conductive particles are 2 times or more the average particle diameters of the conductive particles.

Thermal interface materials deposited in solid form, in a layered manner, and their uses in electronics assembly are described. In one implementation, a method includes: forming an assembly including multiple solid metal thermal interface materials (TIMs) between a first device and a second device such that a first surface of the solid metal TIMs is in touching relation with a surface of the first device, and a second surface of the solid metal TIMs opposite the first surface is in touching relation with a surface of the second device, the solid metal TIMs including a first solid metal TIM and a second solid metal TIM; and forming a liquid TIM alloy from the solid metal TIMs by heating the assembly above a first solidus temperature of the first solid metal TIM, the liquid TIM alloy having a second solidus temperature below the first solidus temperature.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A power module packaging structure includes a first conducting layer, a first insulating layer, a second conducting layer, a first power device, and a first controlling device. The first insulating layer is disposed above the first conducting layer. The second conducting layer is disposed above the first insulating layer. The first power device is disposed on the first conducting layer. The first controlling device is disposed on the second conducting layer and used for controlling the first power device. The first conducting layer, the second conducting layer, the first power device, and the first controlling device form a loop. A direction of a current which flows through the first conducting layer in the loop is opposite to a direction of a current which flows through the second conducting layer in the loop.

A power module packaging structure includes a first conducting layer, a first insulating layer, a second conducting layer, a first power device, and a first controlling device. The first insulating layer is disposed above the first conducting layer. The second conducting layer is disposed above the first insulating layer. The first power device is disposed on the first conducting layer. The first controlling device is disposed on the second conducting layer and used for controlling the first power device. The first conducting layer, the second conducting layer, the first power device, and the first controlling device form a loop. A direction of a current which flows through the first conducting layer in the loop is opposite to a direction of a current which flows through the second conducting layer in the loop.

An anisotropic conductive film that can be produced in high productivity and can reduce a short circuit occurrence ratio has a first conductive particle layer in which conductive particles are dispersed at a predetermined depth in a film thickness direction, and a second conductive particle layer in which conductive particles are dispersed at a depth different from that in the first conductive particle layer. In the respective conductive particle layers, the closest distances between the adjacent conductive particles are 2 times or more the average particle diameters of the conductive particles.