A semiconductor device includes a plurality of islands, each having an outer surface including an upper surface and end surfaces, semiconductor chips, above the respective islands, a bonding material, between the islands and the semiconductor chips, and plating layers, formed on the outer surfaces of the islands, and with at least one of the plurality of islands, the island is exposed as a bare surface region at a first end surface, which, among the end surfaces of the one island, faces the island adjacent thereto.

A light receiving element includes: a semiconductor layer including a first layer, a light absorbing layer, a second layer, and a third layer, the semiconductor layer having a plurality of mesas, a terrace, and a groove; a first electrode provided on the mesas and electrically connected to the third layer; a first bump provided on the first electrode and electrically connected to the first electrode; a second electrode provided on a portion extending from the terrace to an inner side of the groove and electrically connected to the first layer; and a second bump larger than the first bump, is provided on the terrace, and is electrically connected to the second electrode, wherein the mesas and the terrace include the semiconductor layer, the groove extends to the first layer, and the second electrode is in contact with the first layer on an inner side of the groove.

A light receiving element includes: a semiconductor layer including a first layer, a light absorbing layer, a second layer, and a third layer, the semiconductor layer having a plurality of mesas, a terrace, and a groove; a first electrode provided on the mesas and electrically connected to the third layer; a first bump provided on the first electrode and electrically connected to the first electrode; a second electrode provided on a portion extending from the terrace to an inner side of the groove and electrically connected to the first layer; and a second bump larger than the first bump, is provided on the terrace, and is electrically connected to the second electrode, wherein the mesas and the terrace include the semiconductor layer, the groove extends to the first layer, and the second electrode is in contact with the first layer on an inner side of the groove.

A semiconductor device includes a plurality of islands, each having an outer surface including an upper surface and end surfaces, semiconductor chips, above the respective islands, a bonding material, between the islands and the semiconductor chips, and plating layers, formed on the outer surfaces of the islands, and with at least one of the plurality of islands, the island is exposed as a bare surface region at a first end surface, which, among the end surfaces of the one island, faces the island adjacent thereto.

A method of fabricating a thin film transistor structure is described. The method forms a photoresist pattern layer on an active pattern layer and a part of a gate insulating layer to expose a source predetermining position and a drain predetermining position of the gate insulating layer. The photoresist pattern layer has a plurality of inverted trapezoidal blocks which can be used as a mask, thereby depositing a metal layer on the photoresist pattern layer, the source predetermining position and the drain predetermining position. After removing the photoresist pattern layer and the metal layer thereon, the remaining metal layer is patterned to form a source and a drain. In the method of fabricating a thin film transistor structure, a fabricating process can be simplified, and it is unnecessary to form an etching stop layer to protect a back channel.

One example includes an electronic circuit package. The electronic circuit package includes a lead frame. The electronic circuit package includes an electronic circuit die disposed on the lead frame. The electronic circuit package includes a metal plate structure formed on the electronic circuit die, the metal plate structure comprising an aperture that extends through the metal plate structure from a first surface coupled to the electronic circuit die to a second surface opposite the first surface, and further comprising a tapered foot portion formed around a periphery of the metal plate structure at the first surface. The electronic circuit package includes a molding material covering the electronic circuit die around the metal plate structure.

A method for forming an integrated circuit (IC) is provided. In one example, the method includes applying a stencil to an interconnect. The stencil includes a number of openings corresponding to interconnect locations. The method also includes applying an adhesive to the interconnect through the number of openings to form an adhesive layer at an interconnect location of the interconnect locations. The method further includes performing a first cure of the adhesive layer. The method yet further includes attaching a die to the interconnect at the at least one interconnect location. The adhesive layer electrically insulates the die from the interconnect. The method includes performing a second cure of the adhesive layer.