Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.

In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

Methods of semiconductor processing may include contacting a substrate with a first slurry and a first platen. The substrate may include silicon oxide defining one or more features, a liner extending across the silicon oxide and within the one or more features, and a copper-containing layer deposited on the liner and extending within the one or more features. The first slurry and the first platen may remove a first portion of the copper-containing layer. The methods may include contacting the substrate with a second slurry and a second platen, which may remove at least a portion of the liner. The methods may include contacting the substrate with a third slurry and a third platen, which may remove a second portion of the copper-containing layer. The methods may include contacting the substrate with a fourth slurry and a fourth platen, which may remove at least a portion of the silicon oxide.

Provided is a die stack structure including a first die and a second die. The first die and the second die are bonded together through a hybrid bonding structure. At least one of a first test pad of the first die or a second test pad of the second die has a protrusion of the at least one of the first test pad or the second test pad, and a bonding insulating layer of the hybrid bonding structure covers and contacts with the protrusion, so that the first test pad and the second test pad are electrically isolated from each other.

A method of manufacturing a die stack structure includes the following steps. A first bonding structure is formed over a front side of a first die. The method of forming the first bonding structure includes the following steps. A first bonding dielectric material is formed on a first test pad of the first die. A first blocking layer is formed over the first bonding dielectric material. A second bonding dielectric material and a first dummy metal layer are formed over the first blocking layer. The first dummy metal layer and the first test pad are electrically isolated from each other by the first blocking layer. Thereafter, a second bonding structure is formed over a front side of a second die. The first die and the second die are bonded through the first bonding structure and the second bonding structure.

Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.

A light-emitting diode (LED) array is formed by bonding an LED chip or wafer to a backplane substrate via curved interconnects. The backplane substrate may include circuits for driving the LED's. One or more curved interconnects are formed on the backplane substrate. A curved interconnect may be electrically connected to a corresponding circuit of the backplane substrate, and may include at least a portion with curvature. The LED chip or wafer may include one or more LED devices. Each LED device may have one or more electrical contacts. The LED chip or wafer is positioned above the backplane substrate to spatially align electrical contacts of the LED devices with the curved interconnects on the backplane substrate. The electrical contacts are bonded to the curved interconnects to electrically connect the LED devices to corresponding circuits of the backplane substrate.

In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.

In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.