A semiconductor device (1) according to the present disclosure includes a semiconductor chip (2), an interposer substrate (3), and a die-bonding material (4) formed in a partially opened annular shape in a plan view. The semiconductor chip (2) includes a region in which an integration density of an electronic circuit is high (23, 24, and 25) and a region in which the integration density is low (22). The semiconductor chip (2) is implemented on the interposer substrate (3). The die-bonding material (4) formed in a partially opened annular shape in a plan view is provided between the region in which the integration density is high (23, 24, and 25) in the semiconductor chip (2) and the interposer substrate (3).

A bus bar for a power semiconductor module arrangement includes a first end, and a second end. The first end is configured to be arranged inside a housing of the power semiconductor module arrangement. The second end is configured to be arranged outside of the housing and to be electrically contacted by an external bus bar. The second end includes a structured area that includes a plurality of protrusions. A height of each of the protrusions is between 10 μm and 1000 μm.

A method of processing a semiconductor substrate is provided. The method may include forming a film over a first side of a semiconductor substrate, forming at least one separation region in the semiconductor substrate between a first region and a second region of the semiconductor substrate, arranging the semiconductor substrate on a breaking device, wherein the breaking device comprises a breaking edge, and wherein the semiconductor substrate is arranged with the film facing the breaking device and in at least one alignment position with the at least one separation region aligned with the breaking edge, and forcing the semiconductor substrate to bend the first region with respect to the second region over the breaking edge until the film separates between the breaking edge and the at least one separation region.

A semiconductor package includes a carrier, a package module and a second package body. The package module is disposed on the carrier and includes a first substrate, a first electronic element, a first conductive wire and a first package body. The first substrate has a first electrical surface facing the carrier and a second electrical surface opposite to the first electrical surface. The first electronic element is disposed on the first electrical surface. The first conductive wire connects the electronic element with the first electrical surface of the first substrate. The first package body encapsulates the first electrical surface, the first electronic element and the first solder wire. The second package body encapsulates the package module and a portion of the carrier.

Semiconductor device packages may include a bottom-most semiconductor die, at least one intermediate semiconductor die stacked over the bottom-most semiconductor die, and a top-most semiconductor die located on a side of a farthest intermediate semiconductor die from the bottom-most semiconductor die opposite the bottom-most semiconductor die. The bottom-most semiconductor die and each intermediate semiconductor die may include vias extending therethrough. The bottom-most semiconductor die may have a larger foot print than each intermediate semiconductor die and the top-most semiconductor die. A dielectric material may be located between each of the semiconductor dice, at least sections of the dielectric material extending contiguously from between adjacent semiconductor dice, over sidewalls thereof, and laterally beyond the lateral peripheries all but the bottom-most semiconductor die

A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes a semiconductor substrate, a metal pad, a bump, a metal barrier layer, and a solder layer. The metal pad is arranged on the semiconductor substrate; the bump is arranged on the metal pad; the metal barrier layer is arranged on the side of the bump away from the metal pad; the metal barrier layer contains a storage cavity; the sidewall of the metal barrier layer is configured with an opening connecting to the storage cavity; the solder layer is arranged inside the storage cavity, and the top side of the solder layer protrudes from the upper side of storage cavity. During the flip-chip soldering process, solder is heated to overflow, the opening allows the solder flow out through the opening. The openings achieve good solder diversion in overflow, thus mitigating the problem of solder bridging between bumps.

A platform for hermetic heterogeneous integration of passive and active electronic components is provided herein. The platform can include a substrate that provides a hermetic electrical interconnection between integrated circuits and passive devices, such as resistors, capacitors, and inductors. Such substrates can be formed of a dielectric, such as a ceramic, and include electrical interconnects and can further include one or more passive devices. The substrate can include one or more cavities, at least a primary cavity dimensioned to receive an active device and one or more secondary cavities can be included for secondary connector pads for interfacing with the active and passive devices and which can be separately hermetically sealed. The substrate can include a multi-coil inductor defined within alternating layers of the substrate within sidewalls that surround the primary cavity to minimize size of the device package while optimizing the size of the coil.

A platform for hermetic heterogeneous integration of passive and active electronic components is provided herein. The platform can include a substrate that provides a hermetic electrical interconnection between integrated circuits and passive devices, such as resistors, capacitors, and inductors. Such substrates can be formed of a dielectric, such as a ceramic, and include electrical interconnects and can further include one or more passive devices. The substrate can include one or more cavities, at least a primary cavity dimensioned to receive an active device and one or more secondary cavities can be included for secondary connector pads for interfacing with the active and passive devices and which can be separately hermetically sealed. The substrate can include a multi-coil inductor defined within alternating layers of the substrate within sidewalls that surround the primary cavity to minimize size of the device package while optimizing the size of the coil.

Semiconductor device packages may include a bottom-most semiconductor die, at least one intermediate semiconductor die stacked over the bottom-most semiconductor die, and a top-most semiconductor die located on a side of a farthest intermediate semiconductor die from the bottom-most semiconductor die opposite the bottom-most semiconductor die. The bottom-most semiconductor die and each intermediate semiconductor die may include vias extending therethrough. The bottom-most semiconductor die may have a larger foot print than each intermediate semiconductor die and the top-most semiconductor die. A dielectric material may be located between each of the semiconductor dice, at least sections of the dielectric material extending contiguously from between adjacent semiconductor dice, over sidewalls thereof, and laterally beyond the lateral peripheries all but the bottom-most semiconductor die

A semiconductor device includes a redistribution structure, an integrated circuit package attached to a first side of the redistribution structure and a core substrate coupled to a second side of the redistribution structure with a first conductive connector and a second conductive connector. The second side is opposite the first side. The semiconductor device further includes a top layer of the core substrate including a dielectric material and a chip disposed between the redistribution structure and the core substrate. The chip is interposed between sidewalls of the dielectric material.