A semiconductor device manufacturing method includes preparing a semiconductor chip and a conductive plate having a front surface that includes a disposition area on which the semiconductor chip is to be disposed, forming a supporting portion in a periphery of the disposition area of the conductive plate such that the supporting portion protrudes from a bottom of the disposition area in an upward direction orthogonal to the front surface of the conductive plate, bonding the semiconductor chip to the disposition area via bonding material applied to the disposition area, coating the front surface of the conductive plate, including the semiconductor chip and the supporting portion, with a coating layer, and after the coating, sealing the front surface of the conductive plate, including the semiconductor chip and the supporting portion, with sealing material.

Processes of joining substrates via transient liquid phase bonding (TLPB). The processes include providing an interlayer of a low melting temperature phase (LTP) that includes Sn and Bi between and in contact with at least two substrates, and heating the substrates and the interlayer therebetween at a processing temperature equal to or above 200° C. such that the interlayer liquefies and the LTP interacts with high melting temperature phases (HTPs) of the substrates to yield isothermal solidification of the interlayer. The processing temperature is maintained for a duration sufficient for the interlayer to be completely consumed and a solid bond is formed between the substrates. Also provided are assemblies formed by the above noted processes.

Processes of joining substrates via transient liquid phase bonding (TLPB). The processes include providing an interlayer of a low melting temperature phase (LTP) that includes Sn and Bi between and in contact with at least two substrates, and heating the substrates and the interlayer therebetween at a processing temperature equal to or above 200° C. such that the interlayer liquefies and the LTP interacts with high melting temperature phases (HTPs) of the substrates to yield isothermal solidification of the interlayer. The processing temperature is maintained for a duration sufficient for the interlayer to be completely consumed and a solid bond is formed between the substrates. Also provided are assemblies formed by the above noted processes.

Embodiments include a wafer-on-wafer bonding where each wafer includes a seal ring structure around die areas defined in the wafer. Embodiments provide a further seal ring spanning the interface between the wafers. Embodiments may extend the existing seal rings of the wafers, provide an extended seal ring structure separate from the existing seal rings of the wafers, or combinations thereof.

Embodiments include a wafer-on-wafer bonding where each wafer includes a seal ring structure around die areas defined in the wafer. Embodiments provide a further seal ring spanning the interface between the wafers. Embodiments may extend the existing seal rings of the wafers, provide an extended seal ring structure separate from the existing seal rings of the wafers, or combinations thereof.

A method includes forming a first tacking layer on a first connection partner, arranging a first layer on the first tacking layer, forming a second tacking layer on the first layer, arranging a second connection partner on the second tacking layer, heating the tacking layers and first layer, and pressing the first connection partner towards the second connection partner, with the first layer arranged between the connection partners, such that a permanent mechanical connection is formed between the connection partners. Either the tacking layers each include a second material evenly distributed within a first material, the second material being configured to act as or to release a reducing agent, or the tacking layers each include a mixture of at least a third material and a fourth material, the materials in the mixture chemically reacting with each other under the influence of heat such that a reducing agent is formed.

A method includes forming a first tacking layer on a first connection partner, arranging a first layer on the first tacking layer, forming a second tacking layer on the first layer, arranging a second connection partner on the second tacking layer, heating the tacking layers and first layer, and pressing the first connection partner towards the second connection partner, with the first layer arranged between the connection partners, such that a permanent mechanical connection is formed between the connection partners. Either the tacking layers each include a second material evenly distributed within a first material, the second material being configured to act as or to release a reducing agent, or the tacking layers each include a mixture of at least a third material and a fourth material, the materials in the mixture chemically reacting with each other under the influence of heat such that a reducing agent is formed.

Embodiments include a wafer-on-wafer bonding where each wafer includes a seal ring structure around die areas defined in the wafer. Embodiments provide a further seal ring spanning the interface between the wafers. Embodiments may extend the existing seal rings of the wafers, provide an extended seal ring structure separate from the existing seal rings of the wafers, or combinations thereof.

Embodiments include a wafer-on-wafer bonding where each wafer includes a seal ring structure around die areas defined in the wafer. Embodiments provide a further seal ring spanning the interface between the wafers. Embodiments may extend the existing seal rings of the wafers, provide an extended seal ring structure separate from the existing seal rings of the wafers, or combinations thereof.

A semiconductor die includes a silicon carbide (SiC) substrate and a metal stack. The SiC substrate has a first surface including a semiconductor layer thereon and a second surface that is opposite the first surface. The metal stack has an upper surface that attaches to the second surface of the SiC substrate and a lower surface that is opposite the upper surface. The metal stack includes a eutectic solder layer and a noble metal layer on the eutectic solder layer. The noble metal layer comprises a final metal layer on the lower surface.