A method of manufacturing a semiconductor device, the method including: preparing an insulated circuit substrate including a conductive plate; partially fixing a plate-like bonding member onto the conductive plate so as to make a positioning of the bonding member in a horizontal direction; mounting a semiconductor chip on the bonding member; and heating and melting the bonding member so as to form a bonding layer for bonding the insulated circuit substrate and the semiconductor chip each other.

A method of manufacturing a semiconductor device, the method including: preparing an insulated circuit substrate including a conductive plate; partially fixing a plate-like bonding member onto the conductive plate so as to make a positioning of the bonding member in a horizontal direction; mounting a semiconductor chip on the bonding member; and heating and melting the bonding member so as to form a bonding layer for bonding the insulated circuit substrate and the semiconductor chip each other.

A solder material may include nickel and tin. The nickel may include first and second amounts of particles. A sum of the particle amounts is a total amount of nickel or less. The first amount is between 5 at % and 60 at % of the total amount of nickel. The second amount is between 10 at % and 95 at % of the total amount of nickel. The particles of the first amount have a first size distribution, the particles of the second amount have a second size distribution, 30% to 70% of the first amount have a particle size in a range of about 5 μm around a particle size the highest number of particles have according to the first size distribution, and 30% to 70% of the second amount have a particle size in a range of about 5 μm around a particle size the highest number of particles have according to the second size distribution.

An electronic component includes a lead frame; a semiconductor chip arranged above the lead frame; and a connection layer sequence arranged between the lead frame and the semiconductor chip, wherein the connection layer sequence includes a first intermetallic layer including gold and indium or gold, indium and tin, a second intermetallic layer including indium and a titanium compound, indium and nickel, indium and platinum or indium and titanium, and a third intermetallic layer including indium and gold.

An electronic component includes a lead frame; a semiconductor chip arranged above the lead frame; and a connection layer sequence arranged between the lead frame and the semiconductor chip, wherein the connection layer sequence includes a first intermetallic layer including gold and indium or gold, indium and tin, a second intermetallic layer including indium and a titanium compound, indium and nickel, indium and platinum or indium and titanium, and a third intermetallic layer including indium and gold.

A layer structure includes a first layer including at least one material selected from a first group consisting of nickel, copper, gold, silver, palladium, tin, zinc, platinum, and an alloy of any of these materials; a third layer including at least one material selected from a second group consisting of nickel, copper, gold, palladium, tin, silver, zinc, platinum, and an alloy of any of these materials; and a second layer between the first layer and the third layer. The second layer consists of or essentially consists of nickel and tin. The second layer includes an intermetallic phase of nickel and tin.

A display panel includes a pixel array substrate, a plurality of vertical light emitting devices and a flip-chip light emitting device. The pixel array substrate has a first pixel area and a second pixel area. The vertical light emitting devices are disposed in the first pixel area and the second pixel area and electrically connected to the pixel array substrate. The flip-chip light emitting device is disposed in the second pixel area and electrically connected to the pixel array substrate. A color of an emitted light beam of the flip-chip light emitting device and a color of an emitted light beam of one of the vertical light emitting devices located in the first pixel area are identical.

A method for integrating III-V semiconductor materials onto a rigid host substrate deposits a thin layer of reactive metal film on the rigid host substrate. The layer can also include a separation layer of unreactive metal or dielectric, and can be patterned. The unreactive metal pattern can create self-aligned device contacts after bonding is completed. The III-V semiconductor material is brought into contact with the thin layer of reactive metal. Bonding is by a low temperature heat treatment under a compressive pressure. The reactive metal and the functional semiconductor material are selected to undergo solid state reaction and form a stable alloy under the low temperature heat treatment without degrading the III-V material. A semiconductor device of the invention includes a functional III-V layer bonded to a rigid substrate via an alloy of a component of the functional III-V layer and a metal that bonds to the rigid substrate.

A sintering paste includes solvent and nanomicrocrystallite (NMC) particles. Each NMC particle is a single crystallite having at least one dimension in the range of 1 nm to 100 nm and at least one dimension in the range of 0.1 μm to 1000 μm. The sintering paste may be used in a pressureless sintering process to form a low porosity joint having high bond strength, high electrical and thermal conductivity, and high thermal stability.

A die and substrate assembly is disclosed for a die with electronic circuitry and a substrate. A sintered bonding layer of sintered metal is disposed between the die and the substrate. The sintered bonding layer includes a plurality of zones having different sintered metal densities. The plurality of zones are distributed along one or more horizontal axes of the sintered bonding layer, along one or more vertical axes of the sintered bonding layer or along both one or more horizontal and one or more vertical axes of the sintered bonding layer.