An electronic system is disclosed. In one example, the electronic system comprises an at least partially electrically conductive carrier, an electronic component, and an intermetallic connection structure connecting the carrier and the component. The intermetallic connection structure comprising an intermetallic mesh structure in a central portion of the intermetallic connection structure, and opposing exterior structures without intermetallic mesh and each arranged between the intermetallic mesh structure and the carrier or the component.

There is provided a bonding material which forms a bonding portion between two objects, which material contains (1) first metal particles comprising a first metal and having a median particle diameter in the range of 20 nm to 1 μm, and (2) second metal particles comprising, as a second metal, at least one alloy of Sn and at least one selected from Bi, In and Zn and having a melting point of not higher than 200° C.

A method of soldering elements together includes providing a substrate having a metal die attach surface, providing a semiconductor die that is configured as a power semiconductor device and having a semiconductor body, a rear side metallization, and a front side layer stack, the front side layer stack having a front side metallization and a contaminant protection layer, arranging the semiconductor die on the substrate with a region of solder material between the die attach surface and the rear side metallization, and performing a soldering process that reflows the region of solder material to form a soldered joint between the metal die attach surface and the rear side metallization, wherein the soldering process comprises applying mechanical pressure to the front side metallization.

A semiconductor device includes a semiconductor chip having first and second main electrodes disposed on opposite surfaces of a silicon carbide substrate, first and second heat dissipation members disposed so as to sandwich the semiconductor chip, and joining members disposed between the first main electrode and the first heat dissipation member and between the second main electrode and the second heat dissipation member. At least one of the joining members is made of a lead-free solder having an alloy composition that contains 3.2 to 3.8 mass % Ag, 0.6 to 0.8 mass % Cu, 0.01 to 0.2 mass % Ni, x mass % Sb, y mass % Bi, 0.001 to 0.3 mass % Co, 0.001 to 0.2 mass % P, and a balance of Sn, where x and y satisfy relational expressions of x+2y≤11 mass %, x+14y≤42 mass %, and x≥5.1 mass %.

Provided is a method of manufacturing a semiconductor having a double-sided substrate including preparing a first substrate on which a specific pattern is formed to enable electrical connection, preparing at least one semiconductor chip bonded to a metal post, bonding the at least one semiconductor chip to the first substrate, bonding a second substrate to the metal post, forming a package housing by packaging the first substrate and the second substrate to expose a lead frame, and forming terminal leads toward the outside of the package housing. Accordingly, the semiconductor chip and the metal post are previously joined to each other and are respectively bonded to the first substrate and the second substrate so that damage generated while bonding the semiconductor chip may be minimized and electrical properties and reliability of the semiconductor chip may be improved.

A composition exhibits excellent heat resistance and mounting reliability when bonding a semiconductor power element to a metal lead frame, which is also free of lead and thereby places little burden on the environment. An electrically conductive composition contains at least a sulfide compound represented by R—S—R′ (wherein R is an organic group containing at least carbon; R′ is an organic group that is the same as or different from R; and R and R′ may be bonded to each other to form a so-called cyclic sulfide) and metal particles containing at least Cu, Sn or Ni as its essential component. Further, a conductive paste and a conductive bonding film each are produced using the electrically conductive composition. A dicing die bonding film is obtained by bonding the conductive bonding film with an adhesive tape.

A semiconductor assembly includes a substrate including a metal die attach surface, a semiconductor die that is arranged on the substrate, the semiconductor die being configured as a power semiconductor device and comprising a semiconductor body, a rear side metallization, and a front side layer stack, the front side layer stack comprising a front side metallization and a contaminant protection layer that is between the front side metallization and the semiconductor body, and a diffusion soldered joint between the metal die attach surface and the rear side metallization, the diffusion soldered joint comprising one or more intermetallic phases throughout the diffusion soldered joint, wherein the contaminant protection layer is configured to prevent transmission of contaminants into the semiconductor body.

A semiconductor device includes: a semiconductor element; a joined member that is joined to the semiconductor element and includes a nickel film; and a joining layer that is joined to the joined member and contains 2.0 wt % or higher of copper, in which the joining layer includes a solder portion and a Cu.sub.6Sn.sub.5 portion, base metal of the solder portion contains at least tin as a constituent element and contains elemental copper, and the Cu.sub.6Sn.sub.5 portion is in contact with the nickel film.

A semiconductor device includes: a semiconductor element; a joined member that is joined to the semiconductor element and includes a nickel film; and a joining layer that is joined to the joined member and contains 2.0 wt % or higher of copper, in which the joining layer includes a solder portion and a Cu.sub.6Sn.sub.5 portion, base metal of the solder portion contains at least tin as a constituent element and contains elemental copper, and the Cu.sub.6Sn.sub.5 portion is in contact with the nickel film.

Various apparatus and methods are disclosed. In one aspect, a method of manufacturing a thermal interface material on a semiconductor chip is provided. The method includes placing a preform of a combination of a first metal and a second metal on one of the semiconductor chip or a lid. The preform is liquid phase sintered to cause the combination to evolve to an equilibrium composition and bond to the semiconductor chip.