Patent classifications
H01L2224/29298
Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary Substrate
A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices.
HEAT CONDUCTIVE PASTE AND METHOD FOR PRODUCING THE SAME
A heat conductive paste including silver fine particles having an average particle diameter of primary particles of 40 to 350 nm, a crystallite diameter of 20 to 70 nm, and a ratio of the average particle diameter to the crystallite diameter of 1 to 5, an aliphatic primary amine and a compound having at least one phosphoric acid group. The heat conductive paste includes 1 to 40 parts by mass of the aliphatic primary amine and 0.001 to 2 parts by mass of the compound having at least one phosphoric acid group based on 100 parts by mass of the silver fine particles. The heat conductive paste has a high conductivity.
Solder material with two different size nickel particles
A solder material may include nickel and tin. The nickel may include first and second amounts of particles. A sum of the particle amounts is a total amount of nickel or less. The first amount is between 5 at % and 60 at % of the total amount of nickel. The second amount is between 10 at % and 95 at % of the total amount of nickel. The particles of the first amount have a first size distribution, the particles of the second amount have a second size distribution, 30% to 70% of the first amount have a particle size in a range of about 5 μm around a particle size the highest number of particles have according to the first size distribution, and 30% to 70% of the second amount have a particle size in a range of about 5 μm around a particle size the highest number of particles have according to the second size distribution.
QFN Device Having A Mechanism That Enables An Inspectable Solder Joint When Attached To A PWB And Method Of Making Same
An apparatus and method for providing an artificial standoff to the bottom of leads on a QFN device sufficient to provide a gap that changes the fluid dynamics of solder flow and create a unique capillary effect that drives solder up the of leads of a QFN device when it is attached to a printed wiring board (PWB).
PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
A package structure is provided. The package structure includes an interposer substrate including an insulating structure, a conductive pad, a first conducive line, and a first conductive via structure. The package structure includes an electronic device bonded to the conductive pad. The package structure includes a chip structure bonded to the first end portion of the first conductive via structure. The package structure includes a first conductive bump connected between the chip structure and the first end portion of the first conductive via structure. The first end portion protrudes into the first conductive bump and is in direct contact with the first conductive bump.
QFN device having a mechanism that enables an inspectable solder joint when attached to a PWB and method of making same
An apparatus and method for providing an artificial standoff to the bottom of leads on a QFN device sufficient to provide a gap that changes the fluid dynamics of solder flow and create a unique capillary effect that drives solder up the of leads of a UN device when it is attached to a printed wiring board (PWB).
SEMICONDUCTOR DEVICE PACKAGE
A semiconductor device package includes a carrier, a first conductive post and a first adhesive layer. The first conductive post is disposed on the carrier. The first conductive post includes a lower surface facing the carrier, an upper surface opposite to the lower surface and a lateral surface extended between the upper surface and the lower surface. The first adhesive layer surrounds a portion of the lateral surface of the first conductive post. The first adhesive layer comprises conductive particles and an adhesive. The first conductive post has a height measured from the upper surface to the lower surface and a width. The height is greater than the width.
LAYER STRUCTURE AND CHIP PACKAGE THAT INCLUDES THE LAYER STRUCTURE
A layer structure includes a first layer including at least one material selected from a first group consisting of nickel, copper, gold, silver, palladium, tin, zinc, platinum, and an alloy of any of these materials; a third layer including at least one material selected from a second group consisting of nickel, copper, gold, palladium, tin, silver, zinc, platinum, and an alloy of any of these materials; and a second layer between the first layer and the third layer. The second layer consists of or essentially consists of nickel and tin. The second layer includes an intermetallic phase of nickel and tin.
Apparatus and method for securing components of an integrated circuit
Systems and methods of securing an integrated circuit assembly includes: arranging a plurality of securing elements within a plurality of orifices fabricated within one or more layer components of a plurality of layer components of an integrated circuit assembly; applying a mechanical compression load against the integrated circuit assembly that uniformly compresses together the plurality of layer components of the integrated circuit assembly; after applying the mechanical compression load to the integrated circuit assembly, fastening the plurality of securing elements while the integrated circuit assembly is in a compressed state based on the mechanical compression load; and terminating the application of the mechanical compression load against the integrated circuit assembly based on the fastening of the plurality of securing elements.
Semiconductor device package
A semiconductor device package includes a carrier, a first conductive post and a first adhesive layer. The first conductive post is disposed on the carrier. The first conductive post includes a lower surface facing the carrier, an upper surface opposite to the lower surface and a lateral surface extended between the upper surface and the lower surface. The first adhesive layer surrounds a portion of the lateral surface of the first conductive post. The first adhesive layer comprises conductive particles and an adhesive. The first conductive post has a height measured from the upper surface to the lower surface and a width. The height is greater than the width.