A bonding structure formed on a substrate includes an indium layer and a passivating nickel plating formed on the indium layer. The nickel plating serves to prevent a reaction involving the indium layer.

A bonding structure is provided, wherein the bonding structure includes a first substrate, a second substrate, a first adhesive layer, a second adhesive layer, and a silver feature. The second substrate is disposed opposite to the first substrate. The first adhesive layer is disposed on the first substrate. The second adhesive layer is disposed on the second substrate and opposite the first adhesive layer. The silver feature is disposed between the first adhesive layer and the second adhesive layer. The silver feature includes a silver nano-twinned structure that includes twin boundaries that are arranged in parallel. The parallel-arranged twin boundaries include 90% or more [111] crystal orientation.

A micro multi-color LED device includes two or more LED structures for emitting a range of colors. The two or more LED structures are vertically stacked to combine light from the two more LED structures. Light from the micro multi-color LED device is emitted horizontally from each of the LED structures and reflected upward via some reflective structures. In some embodiments, each LED structure is connected to a pixel driver and/or a common electrode. The LED structures are bonded together through bonding layers. In some embodiments, planarization layers enclose each of the LED structures or the micro multi-color LED device. In some embodiments, one or more of reflective layers, refractive layers, micro-lenses, spacers, and reflective cup structures are implemented in the device to improve the LED emission efficiency. A display panel comprising an array of the micro tri-color LED devices has a high resolution and a high illumination brightness.

A micro multi-color LED device includes two or more LED structures for emitting a range of colors. The two or more LED structures are vertically stacked to combine light from the two more LED structures. Light from the micro multi-color LED device is emitted substantially vertically upward through each of the LED structures. In some embodiments, each LED structure is connected to a pixel driver and/or a common electrode. The LED structures are bonded together through bonding layers. In some embodiments, planarization layers enclose each of the LED structures or the micro multi-color LED device. In some embodiments, one or more of reflective layers, refractive layers, micro-lenses, spacers, and reflective cup structures are implemented in the device to improve the LED emission efficiency. A display panel comprising an array of the micro tri-color LED devices has a high resolution and a high illumination brightness.

A power electronics module includes a substrate with a substrate metallization layer, which is separated into conducting areas for providing conducting paths for the power electronics module; a semiconductor switch chip bonded with a first power electrode to a first conducting area of the substrate metallization layer; a conductor plate bonded to a second power electrode of the semiconductor switch chip opposite to the first power electrode.

Implementations of a semiconductor package may include a pin coupled to a substrate. The pin may include a titanium sublayer, a nickel sublayer, and one of a silver and tin intermetallic layer or a copper and tin intermetallic layer, the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer having a melting temperature greater than 260 degrees Celsius. The one of the silver and tin intermetallic layer or the copper and tin intermetallic layer may be formed by reflowing a tin layer and one of a silver layer or copper layer with a silver layer of the substrate where the substrate may be directly coupled to the one of the silver and tin intermetallic layer or the copper and tin intermetallic layer. The substrate may include a copper layer that was directly coupled with the silver layer before the reflow.

Methods for bonding substrates used, for example, in substrate-level packaging, are provided herein. In some embodiments, a method for bonding substrates includes: performing electrochemical deposition (ECD) to deposit at least one material on each of a first substrate and a second substrate, performing chemical mechanical polishing (CMP) on the first substrate and the second substrate to form a bonding interface on each of the first substrate and the second substrate, positioning the first substrate on the second substrate so that the bonding interface on the first substrate aligns with the bonding interface on the second substrate, and bonding the first substrate to the second substrate using the bonding interface on the first substrate and the bonding interface on the second substrate.

A bonding structure is provided, wherein the bonding structure includes a first substrate, a second substrate, a first adhesive layer, a second adhesive layer, and a silver feature. The second substrate is disposed opposite to the first substrate. The first adhesive layer is disposed on the first substrate. The second adhesive layer is disposed on the second substrate and opposite the first adhesive layer. The silver feature is disposed between the first adhesive layer and the second adhesive layer. The silver feature includes a silver nano-twinned structure that includes twin boundaries that are arranged in parallel. The parallel-arranged twin boundaries include 90% or more [111] crystal orientation.

A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer is deposited onto the intermediate metal layer and is then reflowed with a silver layer of a substrate to form an intermetallic layer having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump on each of a plurality of exposed pads of a top side of a die, each exposed pad surrounded by a passivation layer, each bump including an intermediate metal layer as described above and a tin layer coupled to the intermediate metal layer is reflowed to form an intermetallic layer.

A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer is deposited onto the intermediate metal layer and is then reflowed with a silver layer of a substrate to form an intermetallic layer having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump on each of a plurality of exposed pads of a top side of a die, each exposed pad surrounded by a passivation layer, each bump including an intermediate metal layer as described above and a tin layer coupled to the intermediate metal layer is reflowed to form an intermetallic layer.