Patent classifications
H01L2224/29687
CHEMICAL BONDING METHOD AND JOINED STRUCTURE
The present invention achieves chemical bonding by means of a joined film made of oxides formed on a joined surface. In a vacuum container, amorphous oxide thin films are respectively formed on smooth surfaces of two substrates, and the two substrates overlap such that the amorphous oxide thin films formed on the two substrates come into contact with each other, thereby causing chemical bonding involving an atomic diffusion at a joined interface between the amorphous oxide thin films to join the two substrates.
BONDED ASSEMBLY CONTAINING DIFFERENT SIZE OPPOSING BONDING PADS AND METHODS OF FORMING THE SAME
A bonded assembly of a primary semiconductor die and a complementary semiconductor die includes first pairs of first primary bonding pads and first complementary bonding pads that are larger in area than the first primary bonding pads, and second pairs of second primary bonding pads and second complementary bonding pads that are smaller in area than the second primary bonding pads.
METHOD OF FORMING CONFINED GROWTH S/D CONTACT WITH SELECTIVE DEPOSITION OF INNER SPACER FOR CFET
A method of manufacturing a semiconductor device includes forming a stack of epitaxially grown layers alternating between a first semiconductor material and a second semiconductor material that is etch selective to the first semiconductor material. Fin structures are formed from the stack. The fin structures include channel structures formed of the first semiconductor material. The channel structures have opposing ends that are uncovered. Sidewall constraints are formed at the opposing ends of the channel structures. Each pair of the sidewall constraints laterally bounds a respective source/drain (S/D) region at a respective end of the channel structures while having a respective top opening for accessing the respective S/D region. S/D structures are formed on the opposing ends of the channel structures by epitaxially growing a third semiconductor material between each pair of the sidewall constraints.
Chemical bonding method and joined structure
A bonded structure includes a first substrate; a second substrate placed opposite to the first substrate; an intermediate layer provided between the first substrate and the second substrate and including a first oxide thin film layered on the first substrate and a second oxide thin film layered on the second substrate; either or both of the first oxide thin film and the second oxide thin film of the intermediate layer being formed of oxide thin films having increased defects; and an interface between the first oxide thin film and the second oxide thin film=being bonded by chemical bonding, and the interface comprising a low-density portion whose density is lower than that of the two oxide thin films.
CHEMICAL BONDING METHOD AND JOINED STRUCTURE
A bonded structure includes a first substrate; a second substrate placed opposite to the first substrate; an intermediate layer provided between the first substrate and the second substrate and including a first oxide thin film layered on the first substrate and a second oxide thin film layered on the second substrate; either or both of the first oxide thin film and the second oxide thin film of the intermediate layer being formed of oxide thin films having increased defects; and an interface between the first oxide thin film and the second oxide thin film=being bonded by chemical bonding, and the interface comprising a low-density portion whose density is lower than that of the two oxide thin films.
Bond materials with enhanced plasma resistant characteristics and associated methods
Several embodiments of the present technology are directed to bonding sheets having enhanced plasma resistant characteristics, and being used to bond to semiconductor devices. In some embodiments, a bonding sheet in accordance with the present technology comprises a base bond material having one or more thermal conductivity elements embedded therein, and one or more etched openings formed around particular regions or corresponding features of the adjacent semiconductor components. The bond material can include PDMS, FFKM, or a silicon-based polymer, and the etch resistant components can include PEEK, or PEEK-coated components.
BOND MATERIALS WITH ENHANCED PLASMA RESISTANT CHARACTERISTICS AND ASSOCIATED METHODS
Several embodiments of the present technology are directed to bonding sheets having enhanced plasma resistant characteristics, and being used to bond to semiconductor devices. In some embodiments, a bonding sheet in accordance with the present technology comprises a base bond material having one or more thermal conductivity elements embedded therein, and one or more etched openings formed around particular regions or corresponding features of the adjacent semiconductor components. The bond material can include PDMS, FFKM, or a silicon-based polymer, and the etch resistant components can include PEEK, or PEEK-coated components.
Bonded assembly containing different size opposing bonding pads and methods of forming the same
A bonded assembly of a primary semiconductor die and a complementary semiconductor die includes first pairs of first primary bonding pads and first complementary bonding pads that are larger in area than the first primary bonding pads, and second pairs of second primary bonding pads and second complementary bonding pads that are smaller in area than the second primary bonding pads.
SEMICONDUCTOR PACKAGE
A semiconductor package includes a buffer die, memory die stack structures sequentially stacked on the buffer die in a vertical direction, each of which includes a base core die and middle core dies stacked on the base core die in the vertical direction, a first mold layer on the base core die of each of the memory die stack structures and on sidewalls of the middle core dies, and a second mold layer on the buffer die, on sidewalls of the base core dies, and on a sidewall of the first mold layer. The buffer die has a first planar area, the base core die has a second planar area smaller than the first planar area, and each of the middle core dies has a third planar area smaller than the second planar area.
SEMICONDUCTOR DEVICES, FABRICATION METHODS THEREOF, AND MEMORY SYSTEMS
Semiconductor devices, fabrication methods thereof and memory systems are provided. In one aspect, a semiconductor device includes chips and a bonding dielectric layer. The chips are stacked along a thickness direction of the chips. The bonding dielectric layer is located between two adjacent ones of the chips. The bonding dielectric layer at least includes a first material and a second material, and thermal conductivity of the second material is greater than thermal conductivity of the first material.