The present disclosure relates to a method for manufacturing a semiconductor package including vacuum-laminating a non-conductive film on a substrate on which a plurality of through silicon vias are provided and bump electrodes are formed, and then performing UV irradiation, wherein an increase in melt viscosity before and after UV irradiation can be adjusted to 30% or less, whereby a bonding can be performed without voids during thermo-compression bonding, and resin-insertion phenomenon between solders can be prevented, fillets can be minimized and reliability can be improved.

The present disclosure relates to a method for manufacturing a semiconductor package including vacuum-laminating a non-conductive film on a substrate on which a plurality of through silicon vias are provided and bump electrodes are formed, and then performing UV irradiation, wherein an increase in melt viscosity before and after UV irradiation can be adjusted to 30% or less, whereby a bonding can be performed without voids during thermo-compression bonding, and resin-insertion phenomenon between solders can be prevented, fillets can be minimized and reliability can be improved.

A semiconductor layout structure includes: active layers, each active layer including a first active area and a second active area arranged adjacent to the first active area, the first active area including first transistor areas spaced apart from each other, the second active area including second transistor areas spaced apart from each other; and gate layers, each gate layer being arranged above a respective active layer, and including at least one first gate structure extending along a first direction, and second gate structures spaced apart from each other in the first direction, and the at least one first gate structure and the second gate structures being arranged adjacent to each other, the at least one first gate structure corresponding to the first transistor areas, and each second gate structure corresponding to a second transistor area.

The present disclosure relates to a method for manufacturing a semiconductor package including vacuum-laminating a non-conductive film on a substrate on which a plurality of through silicon vias are provided and bump electrodes are formed, and then performing UV irradiation, wherein an increase in melt viscosity before and after UV irradiation can be adjusted to 30% or less, whereby a bonding can be performed without voids during thermo-compression bonding, and resin-insertion phenomenon between solders can be prevented, fillets can be minimized and reliability can be improved.

The present disclosure relates to a method for manufacturing a semiconductor package including vacuum-laminating a non-conductive film on a substrate on which a plurality of through silicon vias are provided and bump electrodes are formed, and then performing UV irradiation, wherein an increase in melt viscosity before and after UV irradiation can be adjusted to 30% or less, whereby a bonding can be performed without voids during thermo-compression bonding, and resin-insertion phenomenon between solders can be prevented, fillets can be minimized and reliability can be improved.

A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.