The present disclosure provides devices and methods in which a semiconductor chip has a reduced size and thickness. The device is manufactured by utilizing a sacrificial or dummy silicon wafer. A recess is formed in the dummy silicon wafer where the semiconductor chip is mounted in the recess. The space between the dummy silicon wafer and the chip is filled with underfill material. The dummy silicon wafer and the backside of the chip are etched using any suitable etching process until the dummy silicon wafer is removed, and the thickness of the chip is reduced. With this process, the overall thickness of the semiconductor chip can be thinned down to less than 50 μm in some embodiments. The ultra-thin semiconductor chip can be incorporated in manufacturing flexible/rollable display panels, foldable mobile devices, wearable displays, or any other electrical or electronic devices.

An optical module includes an optical semiconductor chip including a first electrode pad, a second electrode pad, and a third electrode pad arranged between the first electrode pad and the second electrode pad, a wiring substrate on which the optical semiconductor chip is flip-chip mounted, including a fourth electrode pad, a fifth electrode pad, and a sixth electrode pad arranged between the fourth electrode pad and the fifth electrode pad, a first conductive material connecting the first electrode pad with the fourth electrode pad, a second conductive material connecting the second electrode pad with the fifth electrode pad, a third conductive material arranged between the first conductive material and the second conductive material, connecting the third electrode pad with the sixth electrode pad, and a resin provided in an area on the second conductive material side of the third conductive material between the optical semiconductor chip and the wiring substrate.

An electronic device which can suppress peeling off and damaging of the bonding material is provided. The electronic device includes an electronic component, a mounting portion, and a bonding material. The electronic component has an element front surface and an element back surface separated in the z-direction. The mounting portion has a mounting surface opposed to the element back surface on which the electronic component is mounted. The bonding material bonds the electronic component to the mounting portion. The bonding material includes a base portion and a fillet portion. The base portion is held between the electronic component and the mounting portion in the z-direction. The fillet portion is connected to the base portion and is formed outside the electronic component when seen in the z-direction. The electronic component includes two element lateral surface and ridges. The ridges are intersections of the two element lateral surface and extend in the z-direction. The fillet portion includes a ridge cover portion which covers at least a part of the ridges.

Structures and formation methods of a chip package structure are provided. The chip package structure includes an interposer substrate including first and second die regions that are separated by a gap region. The chip package structure also includes first and second semiconductor dies respectively arranged over the first and second die regions. In addition, the chip package structure includes first and second gap-filling layers formed over the gap region and separated from one another, and a third gap-filling layer over the gap region and between the first and second gap-filling layers. The Young's modulus of the third gap-filling layer is less than the Young's modulus of the first gap-filling layer and the Young's modulus of the second gap-filling layer.

A semiconductor arrangement includes a semiconductor substrate having a dielectric insulation layer and at least a first metallization layer arranged on a first side of the dielectric insulation layer. The first metallization layer includes at least two sections, each section being separated from a neighboring section by a recess. A semiconductor body is arranged on one of the sections of the first metallization layer. At least one indentation is arranged between a first side of the semiconductor body and a closest edge of the respective section of the first metallization layer. A distance between the first side and the closest edge of the section of the first metallization layer is between 0.5 mm and 5 mm.

An electronic device includes a substrate, a plurality of micro semiconductor structure, a plurality of conductive members, and a non-conductive portion. The substrate has a first surface and a second surface opposite to each other. The micro semiconductor structures are distributed on the first surface of the substrate. The conductive members electrically connect the micro semiconductor structures to the substrate. Each conductive member is defined by an electrode of one of the micro semiconductor structures and a corresponding conductive pad on the substrate. The non-conductive portion is arranged on the first surface of the substrate. The non-conductive portion includes one or more non-conductive members, and the one or more non-conductive members are attached to the corresponding one or more conductive members of the one or more micro conductive structures.

A semiconductor package including an interposer substrate, first to third semiconductor chips on the interposer substrate to face each other, an underfill part between each of the first to third semiconductor chips and the interposer substrate, a first side-fill part extending upward from a lower end of side walls of the first to third semiconductor chips, and a second side-fill part between the side walls of the first to third semiconductor chips and extending from the first side-fill part to an upper end of the side walls of the first to third semiconductor chips may be provided.

A method for producing a semiconductor arrangement includes: forming a first metallization layer on a first side of a dielectric insulation layer, the first metallization layer having at least two sections, each section being separated from a neighboring section by a recess; arranging a semiconductor body on one of the sections of the first metallization layer; and forming at least one indentation between a first side of the semiconductor body and a closest edge of the respective section of the first metallization layer. A distance between the first side and the closest edge of the section of the first metallization layer is between 0.5 mm and 5 mm.

A semiconductor package may include a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, and an adhesive layer between the first semiconductor chip and the second semiconductor chip. The first semiconductor chip may include a semiconductor substrate and a plurality of protection layers on the semiconductor substrate. The topmost layer of the protection layers may have a top surface with convex portions and concave portions, and the convex portions and the concave portions may be in contact with the adhesive layer.

A package structure and a formation method of a package structure are provided. The method includes disposing a chip structure over a substrate and forming a first adhesive element directly on the chip structure. The first adhesive element has a first thermal conductivity. The method also includes forming a second adhesive element directly on the chip structure. The second adhesive element has a second thermal conductivity, and the second thermal conductivity is greater than the first thermal conductivity. The method further includes attaching a protective lid to the chip structure through the first adhesive element and the second adhesive element.