An electronic device which can suppress peeling off and damaging of the bonding material is provided. The electronic device includes an electronic component, a mounting portion, and a bonding material. The electronic component has an element front surface and an element back surface separated in the z-direction. The mounting portion has a mounting surface opposed to the element back surface on which the electronic component is mounted. The bonding material bonds the electronic component to the mounting portion. The bonding material includes a base portion and a fillet portion. The base portion is held between the electronic component and the mounting portion in the z-direction. The fillet portion is connected to the base portion and is formed outside the electronic component when seen in the z-direction. The electronic component includes two element lateral surface and ridges. The ridges are intersections of the two element lateral surface and extend in the z-direction. The fillet portion includes a ridge cover portion which covers at least a part of the ridges.

A display device includes a substrate including a conductive pad, a driving chip facing the substrate and including a conductive bump electrically connected to the conductive pad and an inspection bump which is insulated from the conductive pad, and an adhesive member which is between the conductive pad and the driving chip and connects the conductive pad to the driving chip. The adhesive member includes a first adhesive layer including a conductive ball, and a second adhesive layer facing the first adhesive layer, the second adhesive layer including a first area including a color-changing material, and a second area adjacent to the first area and excluding the color-changing material.

A semiconductor package includes a package substrate, a first semiconductor chip and a second semiconductor chip sequentially stacked on the package substrate, the first semiconductor chip and the second semiconductor chip being disposed in a form of an offset stack structure, and the second semiconductor chip including an overhang further protruding beyond a side surface of the first semiconductor chip in a first horizontal direction, an adhesive member disposed on a lower surface of the second semiconductor chip, the adhesive member including an extension extending to a lower level than an upper surface of the first semiconductor chip. The extension contacts the side surface of the first semiconductor chip, and overlaps with at least a portion of the overhang in a vertical direction.

A semiconductor package includes; a substrate including a first insulating layer and a first conductive pattern in the first insulating layer, a first semiconductor chip on the substrate, an interposer spaced apart from the first semiconductor chip in a direction perpendicular to an upper surface of the substrate and including a second insulating layer and a second conductive pattern in the second insulating layer, a first element between the first semiconductor chip and the interposer, a connection member between the substrate and the interposer, and a mold layer covering side surfaces of the first semiconductor chip and side surfaces of the first element.

A semiconductor package includes a circuit board including a wiring structure, first and second semiconductor chips disposed on the circuit board and connected to the wiring structure, a dummy chip disposed on the circuit board and positioned between the first and second semiconductor chips, and a molded member disposed on the circuit board and surrounding the first and second semiconductor chips and the dummy chip. The dummy chip may include a rounded edge between an upper surface and a side surface.

Provide is a highly reliable semiconductor device in which stress generated in a semiconductor chip is reduced and an increase in thermal resistance is suppressed. The semiconductor device includes: a semiconductor chip including a first main electrode on one surface thereof and a second main electrode and a gate electrode on the other surface thereof; a first electrode connected to the one surface of the semiconductor chip via a first bonding material; and a second electrode connected to the other surface of the semiconductor chip via a second bonding material. The first electrode is a plate-shaped electrode and has a groove in a region overlapping with the semiconductor chip. The groove penetrates in a thickness direction of the first electrode and reaches an end portion of the first electrode when viewed in a plan view.

A semiconductor device includes: a plurality of semiconductor chips stacked on a substrate in a vertical direction; a filler structure including a plurality of horizontal underfill layers formed between adjacent semiconductor chips of the plurality of semiconductor chips and between the substrate and the stack of semiconductor chips, and including underfill sidewalls formed around the horizontal underfill layers and the plurality of semiconductor chips; and a molding resin surrounding the plurality of semiconductor chips at least on side surfaces of the plurality of semiconductor chips. The underfill sidewalls include a recess pattern, which is disposed on and along the side surfaces of at least one of the plurality of semiconductor chips, and is recessed in a direction parallel to an upper surface of the substrate at locations where the recess pattern meets the substrate.

A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.

Structures and formation methods of a chip package structure are provided. The chip package structure includes an interposer substrate including first and second die regions that are separated by a gap region. The chip package structure also includes first and second semiconductor dies respectively arranged over the first and second die regions. In addition, the chip package structure includes first and second gap-filling layers formed over the gap region and separated from one another, and a third gap-filling layer over the gap region and between the first and second gap-filling layers. The Young's modulus of the third gap-filling layer is less than the Young's modulus of the first gap-filling layer and the Young's modulus of the second gap-filling layer.

A semiconductor package includes a semiconductor chip on a package substrate, a dam structure disposed on the package substrate and surrounding the semiconductor chip, the dam structure including a first dam portion having a first length in a vertical direction, and a second dam portion connected to the first dam portion and extending from an outer side of the first dam portion, and having a second length less than the first length in the vertical direction, and an adhesive layer disposed on the package substrate, the adhesive layer including a first adhesive portion disposed between the semiconductor chip and the package substrate and overlapping the semiconductor chip in the vertical direction, and a second adhesive portion on an outer side of the semiconductor chip and including at least a part contacting a top surface of the first dam portion.