In order to achieve the above-described technical benefits, according to an aspect of the present disclosure, a display device includes a stretchable lower substrate which includes an active area and a non-active area disposed at the outside of the active area; a pattern layer which is disposed on the lower substrate and includes a plurality of plate patterns and a plurality of line patterns; a plurality of pixels which is disposed above each of the plurality of plate patterns in the active area; and a plurality of connection lines which is disposed above the plurality of line patterns to connect the plurality of pixels, and the plurality of connection lines includes a high potential voltage line and a low potential voltage line which overlap each other in each of the plurality of plate patterns.

A display device according to an example embodiment of the present disclosure may include a stretchable lower substrate; a lower pattern layer disposed on the lower substrate and including a plurality of lower plate patterns and a plurality of lower line patterns; a plurality of pixel circuits disposed on each of the plurality of lower plate patterns; a plurality of lower stretched lines disposed on each of the plurality of lower line patterns; an upper pattern layer disposed on the lower pattern layer and including a plurality of upper plate patterns and a plurality of upper line patterns; a plurality of light emitting elements disposed on each of the plurality of upper plate patterns; and a plurality of upper stretched lines disposed on each of the plurality of upper line patterns, so that a uniform power may be supplied.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure including a first substrate, and a first circuit layer positioned on the first substrate, a first redistribution structure positioned on the first circuit layer, and a second semiconductor structure including a second circuit layer positioned on the first redistribution structure, and a second substrate positioned on the second circuit layer. A layout of the first circuit layer and a layout of the second circuit layer are substantially the same and the first redistribution structure is electrically coupled to the first semiconductor structure and the second semiconductor structure.

A semiconductor package includes a first die; a first redistribution structure over the first die, the first redistribution structure being conterminous with the first die; a second die over the first die, a first portion of the first die extending beyond a lateral extent of the second die; a conductive pillar over the first portion of the first die and laterally adjacent to the second die, the conductive pillar electrically coupled to first die; a molding material around the first die, the second die, and the conductive pillar; and a second redistribution structure over the molding material, the second redistribution structure electrically coupled to the conductive pillar and the second die.

Provided is a semiconductor package including a pair of differential signal wiring lines including a first differential signal wiring line and a second differential signal wiring line, extending parallel to and spaced apart from each other, a lower equal potential plate in a lower wiring layer under the signal wiring layer, an upper equal potential plate in an upper wiring layer above the signal wiring layer, and a wiring insulating layer adjacent to the pair of differential signal wiring lines, the lower equal potential plate, and the upper equal potential plate, the wiring insulating layer filling spaces between the signal wiring layer, the lower wiring layer, and the upper wiring layer, at least one of the lower equal potential plate and the upper equal potential plate including an impedance opening overlapping the pair of differential signal wiring lines in a vertical direction and is filled by the wiring insulating layer.

A bonding structure is provided, wherein the bonding structure includes a first substrate, a second substrate, a first adhesive layer, a second adhesive layer, and a silver feature. The second substrate is disposed opposite to the first substrate. The first adhesive layer is disposed on the first substrate. The second adhesive layer is disposed on the second substrate and opposite the first adhesive layer. The silver feature is disposed between the first adhesive layer and the second adhesive layer. The silver feature includes a silver nano-twinned structure that includes twin boundaries that are arranged in parallel. The parallel-arranged twin boundaries include 90% or more [111] crystal orientation.

A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, and a plurality of first through electrodes penetrating at least a portion of the first semiconductor substrate. A plurality of second semiconductors include a second semiconductor substrate, the plurality of second semiconductor chips being stacked on the first semiconductor chip. A plurality of bonding pads are arranged between the first semiconductor chip and the plurality of second semiconductor chips. A chip bonding insulating layer is arranged between the first semiconductor chip and the plurality of second semiconductor chips. At least one supporting dummy substrate is stacked on the plurality of second semiconductor chips and having a support bonding insulating layer arranged on a lower surface thereof.

The present application discloses a method for fabricating a semiconductor device with a connection structure. The method includes providing a first semiconductor structure comprising a plurality of first conductive features adjacent to a top surface of the first semiconductor structure; forming a connection structure comprising a connection insulating layer on the top surface of the first semiconductor structure, a connection layer in the connection insulating layer, and a plurality of first porous interlayers on the plurality of first conductive features and in the connection insulating layer; and forming a second semiconductor structure comprising a plurality of second conductive features on the plurality of first porous interlayers.

Discussed is a semiconductor light emitting device for a display panel, a substrate structure for a display panel, and a display device including the substrate structure. A display device including a semiconductor light emitting device can include a first electrode and a second electrode spaced apart from each other on a predetermined substrate, an insulating layer disposed on the first and second electrodes, a first barrier wall disposed on the insulating layer and including a first assembling hole and a semiconductor light emitting device disposed in the first assembling hole of the first barrier wall. Also, the semiconductor light emitting device can include a light emitting structure, a passivation layer on the light emitting structure, and a first reflective alignment structure disposed in the light emitting structure.

A display device according to an example embodiment of the present disclosure includes a stretchable display panel; and an actuator configured to deform the display panel, wherein the display panel includes a first area that is protruded by the actuator, a second area that is not protruded by the actuator, and a third area that is between the first area and the second area, wherein a plurality of pixels are disposed in the first area and the second area, wherein in the third area, only a plurality of connection lines connecting the plurality of pixels disposed in the first area and the plurality of pixels disposed in the second area are disposed, so that three-dimensional display capability of the display device can be improved.