Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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H01L2224/26
Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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H01L2224/31
Structure, shape, material or disposition of the layer connectors after the connecting process
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H01L2224/32
of an individual layer connector
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H01L2224/32151
the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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H01L2224/32153
the body and the item being arranged next to each other, e.g. on a common substrate
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H01L2224/32153

INTEGRATED CIRCUIT DIES WITH THERMALLY CONDUCTING SOLDER PERIMETER
20240282658 · 2024-08-22 ·

A semiconductor integrated circuit device includes a first back-end-of-line region coupled to a first side of a front-end-of-line region, a second back-end-of-line region coupled to a second side of the front-end-of-line region, and a thermally conducting solder at least partially surrounding a perimeter of the front-end-of-line region, the first back-end-of-line region and the second back-end-of-line region.