A semiconductor package structure includes a first semiconductor wafer including a first bonding pad. The semiconductor package structure also includes a second semiconductor wafer including a second bonding pad and a third bonding pad. The second bonding pad and the third bonding pad are bonded to the first bonding pad of the first semiconductor wafer. The semiconductor package structure further includes a first via penetrating through the second semiconductor wafer to physically contact the first bonding pad of the first semiconductor wafer. A portion of the first via is disposed between the second bonding pad and the third bonding pad.

Provided is a stacked semiconductor package including a package base substrate including a plurality of signal wires and at least one power wire, wherein a plurality of top surface connecting pads and a plurality of bottom surface connecting pads are on a top surface and a bottom surface of the package base substrate, respectively; and a plurality of semiconductor chips that are sequentially stacked on the package base substrate and are electrically connected to the top surface connecting pads, the plurality of semiconductor chips including a first semiconductor chip that is a bottommost semiconductor chip, and a second semiconductor chip that is on the first semiconductor chip, wherein the signal wires are arranged apart from a portion of the package base substrate, the first portion that overlaps a first edge of the first semiconductor chip, the first edge overlapping the second semiconductor chip in a vertical direction.

Various embodiments include a circuit carrier comprising: an installation place for an electronic component; and a deposit of a joining adjuvant applied to the installation place. The installation place has at an edge, a recess forming a depression in a surface of the circuit carrier. The deposit comprises a sintered material with a protuberance at an edge of the deposit.

Provided is a stacked semiconductor package including a package base substrate including a plurality of signal wires and at least one power wire, wherein a plurality of top surface connecting pads and a plurality of bottom surface connecting pads are on a top surface and a bottom surface of the package base substrate, respectively; and a plurality of semiconductor chips that are sequentially stacked on the package base substrate and are electrically connected to the top surface connecting pads, the plurality of semiconductor chips including a first semiconductor chip that is a bottommost semiconductor chip, and a second semiconductor chip that is on the first semiconductor chip, wherein the signal wires are arranged apart from a portion of the package base substrate, the first portion that overlaps a first edge of the first semiconductor chip, the first edge overlapping the second semiconductor chip in a vertical direction.

A semiconductor device and method of manufacture are presented in which a first pad and a second pad are formed adjacent to each other. A first set of dummy pads is manufactured between the first pad and the second pad and bonding pads are formed in electrical connection to the first pad and the second pad.

Provided is a stacked semiconductor package including a package base substrate including a plurality of signal wires and at least one power wire, wherein a plurality of top downsurface connecting pads and a plurality of bottom surface connecting pads are on a top surface and a bottom surface of the package base substrate, respectively; and a plurality of semiconductor chips that are sequentially stacked on the package base substrate and are electrically connected to the top surface connecting pads, the plurality of semiconductor chips including a first semiconductor chip that is a bottommost semiconductor chip, and a second semiconductor chip that is on the first semiconductor chip, wherein the signal wires are arranged apart from a portion of the package base substrate, the first portion that overlaps a first edge of the first semiconductor chip, the first edge overlapping the second semiconductor chip in a vertical direction.

A semiconductor package structure includes a first semiconductor wafer including a first bonding pad. The semiconductor package structure also includes a second semiconductor wafer including a second bonding pad and a third bonding pad. The second bonding pad and the third bonding pad are bonded to the first bonding pad of the first semiconductor wafer. The semiconductor package structure further includes a first via penetrating through the second semiconductor wafer to physically contact the first bonding pad of the first semiconductor wafer. A portion of the first via is disposed between the second bonding pad and the third bonding pad.

Provided is a stacked semiconductor package including a package base substrate including a plurality of signal wires and at least one power wire, wherein a plurality of top surface connecting pads and a plurality of bottom surface connecting pads are on a top surface and a bottom surface of the package base substrate, respectively; and a plurality of semiconductor chips that are sequentially stacked on the package base substrate and are electrically connected to the top surface connecting pads, the plurality of semiconductor chips including a first semiconductor chip that is a bottommost semiconductor chip, and a second semiconductor chip that is on the first semiconductor chip, wherein the signal wires are arranged apart from a portion of the package base substrate, the first portion that overlaps a first edge of the first semiconductor chip, the first edge overlapping the second semiconductor chip in a vertical direction.

A semiconductor package structure includes a first semiconductor wafer including a first bonding pad. The semiconductor package structure also includes a second semiconductor wafer including a second bonding pad and a third bonding pad. The second bonding pad and the third bonding pad are bonded to the first bonding pad of the first semiconductor wafer. The semiconductor package structure further includes a first via penetrating through the second semiconductor wafer to physically contact the first bonding pad of the first semiconductor wafer. A portion of the first via is disposed between the second bonding pad and the third bonding pad.

A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first main body, at least one first columnar portion and at least one first conductive layer. The first columnar portion protrudes from a bottom surface of the first main body. The first conductive layer is disposed on a side surface of the first columnar portion. The second semiconductor device includes a second main body, at least one second columnar portion and at least one second conductive layer. The second columnar portion protrudes from a top surface of the second main body. The second conductive layer is disposed on a side surface of the second columnar portion. The first conductive layer is electrically coupled to the second conductive layer.