A semiconductor module such that warping or distortion is prevented, and reliability can be increased, is obtained. The semiconductor module includes a base configuring a multiple of terminals or wires, a semiconductor switching element mounted on a mounting portion of the terminal, and a molded resin that seals the semiconductor switching element, wherein a wide portion having a width greater than that of the terminal or the wire is formed in one portion of the terminal or the wire in an outer peripheral side end portion of the molded resin, and the wide portion is embedded and fixed in an interior of the molded resin in a state extended toward the interior from the outer peripheral side end portion of the molded resin.

A semiconductor module (1) such that warping or distortion is prevented, and reliability can be increased, is obtained. The semiconductor module (1) includes a base (10a) configuring a multiple of terminals (C1 to C6, B1, B2, M1, M2) or wires (G1, G2), a semiconductor switching element (T1 to T4) mounted on a mounting portion (21) of the terminal (C1 to C6, B1, B2, M1, M2), and a molded resin (20) that seals the semiconductor switching element (T1 to T4), wherein a wide portion (G10, G20) having a width greater than that of the terminal (C1 to C6, B1, B2, M1, M2) or the wire (G1, G2) is formed in one portion of the terminal (C1 to C6, B1, B2, M1, M2) or the wire (G1, G2) in an outer peripheral side end portion of the molded resin (20), and the wide portion (G10, G20) is embedded and fixed in an interior of the molded resin (20) in a state extended toward the interior from the outer peripheral side end portion of the molded resin (20).

A clip structure for a packaged semiconductor device is provided. The packaged semiconductor device includes a first die portion and a second die portion being electrically isolated from the first die portion. The clip structure includes a first portion, a second portion and a gate wire bond. The first portion is electrically conductive, and the first portion is configured to integrally connect a source terminal with the first die portion. The second portion is electrically conductive and is electrically isolated from the first portion and is configured to connect to a gate terminal. The gate wire bond is configured to connect the second portion with the second die portion.

According to one embodiment, a semiconductor device includes: a first frame, a second frame spaced apart from the first frame in a first direction, and a first joint terminal provided above a second chip provided on the second frame. The first frame includes a first terminal portion extending toward the second frame. The first joint terminal includes a second terminal portion extending toward the first frame. The second terminal portion includes a plane portion, a first projecting portion and a second projecting portion each branching out from the plane portion. An end portion of the first projecting portion and an end portion of the second projecting portion are respectively joined on the first terminal portion. The first projecting portion is different in a length in a first direction from the second projecting portion.

A semiconductor device including: a first semiconductor chip having a first power transistor and a temperature sensing diode; and a second semiconductor chip having a second power transistor, but not having a temperature sensing diode.

A die-packaging component includes a substrate, a die, a jumper structure, a lead structure and a package body. The substrate has a base surface further including a die-connecting portion and a package-body retaining structure surrounding the die-connecting portion. The die connects the die-connecting portion. The jumper structure welded to the die generates a thermal deformation while in conducting a high-voltage current. The lead structure includes a lead groove defining a thermal-deformation tolerance allowable route. While in meeting the thermal deformation, the jumper structure welded to the lead groove as well is movable along the thermal-deformation tolerance allowable route. The package body at least partly covers the lead structure and the substrate, completely covers the die and the jumper structure, and is constrained by the package-body retaining structure.

A method for producing a power-electronics switching device and a power electronic switching device produced thereby. In the power-electronics switching device, a power semiconductor component is arranged on a first region of a conductor track of a substrate. An insulating film comprising a cutout is then provided, wherein an overlap region of the insulating film, which overlap region is adjacent to the cutout, is designed to cover an edge region of the power semiconductor component. This is followed by arranging the insulating film on the substrate, with the power semiconductor component arranged on it, in such a way that the power semiconductor component is covered on all sides of its edge region by the covering region of the insulating film, wherein a further section of the insulating film covers parts of one of the conductor tracks. Finally, the connecting device is arranged.

A semiconductor device including: a first semiconductor chip having a first power transistor and a temperature sensing diode; and a second semiconductor chip having a second power transistor, but not having a temperature sensing diode.