Patent classifications
H01L2224/40
DRMOS, INTEGRATED CIRCUIT, ELECTRONIC DEVICE, AND PREPARATION METHOD
A driver metal-oxide-semiconductor field-effect transistor DrMOS, an integrated circuit, an electronic device, and a preparation method are provided. The DrMOS mainly includes a first die and a second die. The first die includes a drive circuit and a first switching transistor, and the drive circuit is connected to a gate of the first switching transistor. The second die includes a second switching transistor, and the drive circuit is connected to a gate of the second switching transistor through a first conductor. The drive circuit and the first switching transistor are prepared in a same die. This helps to reduce an area, loss, and costs of the DrMOS. The first switching transistor and the second switching transistor are prepared in different dies that reduces type selection limitation.
POWER SEMICONDUCTOR MODULE
A power semiconductor module includes a metal bottom plate, an insulating heat dissipation material layer, a chip, a binding plate, silica gel, and an outer housing, where the binding plate includes a copper plate and a copper strap. The copper plate is connected to the copper strap through welding, and the binding plate is configured to connect circuits of various components. The metal bottom plate is connected to the insulating heat dissipation material layer through tin soldering, the chip is connected to the insulating heat dissipation material layer through tin soldering, the chip is connected to the copper strap, and the copper strap is connected to the insulating heat dissipation material layer. The module can resolve the prior-art problem of mechanical stress generated on the chip in the case of a temperature change when a relatively thick copper frame is applied to the packaging of the power semiconductor module.
Terminal Member, Assembly, Semiconductor Device, and Methods for Manufacturing Same
Workability in a manufacturing process of a semiconductor device is improved. A terminal member is the terminal member joined to an electrode of a semiconductor element, and includes a conductor portion, a first annular projecting portion, and an annular recess. The conductor portion has a first main surface and a second main surface located on a side opposite to the first main surface. The first annular projecting portion is provided on the first main surface of the conductor portion. The annular recess is provided on the second main surface and is disposed at a position overlapping with the first annular projecting portion. By pressing a joining member against the first main surface of the terminal member, the first annular projecting portion can be embedded in the joining member.
Semiconductor device
A semiconductor device includes a first conductive plate, a second conductive plate, first switching elements, second switching elements, a first supply terminal and a second supply terminal. The first and second conductive plates are spaced apart from each other in a first direction. The first switching elements are bonded to the first conductive plate, and are electrically connected to the second conductive plate. The second switching elements are bonded to the second conductive plate. The first supply terminal is bonded to the first conductive plate. The second supply terminal has a region that overlaps with the first supply terminal as viewed in a plan view. The second supply terminal is spaced apart from the first conductive plate and the first supply terminal in a thickness direction perpendicular to the first direction. The second supply terminal is electrically connected to the second switching elements.
SEMICONDUCTOR DEVICE
In a semiconductor device, a first skirt portion molded from a first mold resin and a second skirt portion molded from a second mold resin are provided on a heat dissipating surface of a lead frame. Also, a thinly-molded portion is molded integrally with the second skirt portion from the second mold resin. According to this kind of configuration, adhesion between the thinly-molded portion and lead frame is high, and the semiconductor device with excellent heat dissipation and insulation is obtained.
ELECTRONIC PART MOUNTING HEAT-DISSIPATING SUBSTRATE
[Problem] An object of the present invention is to provide an electronic part mounting heat-dissipating substrate which enables a circuit for which a power semiconductor in which a large current flows is used to reduce the wiring resistances of a large power operation and improve the heat dissipation.
[Means for Solving] The present invention is an electronic part mounting heat-dissipating substrate which comprises lead frames of wiring pattern shapes formed by conductor plate and an insulating member 130 which is provided between the lead frames 110, wherein a plate surface of a part arrangement surface of said conductor plate and a top surface of said insulating member at a side of said part arrangement surface form one continuous surface, the lead frames have different thicknesses, the thick lead frame 110H is used for a large current signal and the thin lead frame 110L is used for a small current signal, a plate surface of a back surface of the part arrangement surface and a top surface of the insulating member at a side of the back surface at the part arrangement surface-side are formed in an identical plane.
ELECTRONIC PART MOUNTING HEAT-DISSIPATING SUBSTRATE
[Problem] An object of the present invention is to provide an electronic part mounting heat-dissipating substrate which enables a circuit for which a power semiconductor in which a large current flows is used to reduce the wiring resistances of a large power operation and improve the heat dissipation.
[Means for Solving] The present invention is an electronic part mounting heat-dissipating substrate which comprises lead frames of wiring pattern shapes formed by conductor plate and an insulating member 130 which is provided between the lead frames 110, wherein a plate surface of a part arrangement surface of said conductor plate and a top surface of said insulating member at a side of said part arrangement surface form one continuous surface, the lead frames have different thicknesses, the thick lead frame 110H is used for a large current signal and the thin lead frame 110L is used for a small current signal, a plate surface of a back surface of the part arrangement surface and a top surface of the insulating member at a side of the back surface at the part arrangement surface-side are formed in an identical plane.
Multiple die layout for facilitating the combining of an individual die into a single die
An apparatus includes a wafer portion and a plurality of die fabricated in the wafer portion in a defined pattern such that the die are separated from each other by a dicing area or a street. The apparatus includes a conductive connection between given adjacent die. The conductive connection is electrically coupled to circuitry disposed on the given adjacent die.
SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE
A semiconductor device includes: a semiconductor chip; and an Ag fired cap formed so as to cover a source pad electrode formed on the semiconductor chip. The semiconductor chip is disposed on a first substrate electrode, and one end of a Cu wire is bonded onto the Ag fired cap by means of an ultrasonic wave. There is provided a semiconductor device capable of improving a power cycle capability, and a fabrication method of such a semiconductor device.
POWER CONVERSION APPARATUS AND METHOD FOR MANUFACTURING THE SAME
A second lead frame is set onto a conductive layer and a busbar. The second lead frame has holes previously formed at opposite ends thereof, and pieces of solder material or solder pieces are inserted into the holes. Then, the solder pieces are vibrated by an ultrasonically vibrating tool, whereby the solder pieces are melted without having a high temperature. The second lead frame is thus bonded to the conductive layer and the busbar. A semiconductor element and the busbar are connected by a first lead frame and the second lead frame. The connection structure thereof is such that the second lead frame to be bonded by ultrasonic bonding or other bonding methods is not directly in contact with the semiconductor element, which eliminates the risk of damage to the semiconductor element.