A display device and method for fabrication thereof includes a plurality of pixel electrodes and common electrode connection parts that are spaced from each other on a first substrate, a plurality of light emitting elements on the plurality of pixel electrodes, a plurality of common electrode elements on the common electrode connection parts, and a common electrode layer on the plurality of light emitting elements and the plurality of common electrode elements, wherein each of the plurality of light emitting element includes a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, each of the plurality of common electrode elements includes at least the second semiconductor layer, and the common electrode layer includes a same material as the second semiconductor layer to be connected to the second semiconductor layers of the plurality of light emitting elements.

A method of forming a semiconductor package is provided. The method includes forming a metallization stack over a semiconductor die. Polymer particles are mounted over the metallization stack. Each of the polymer particles is coated with a first bonding layer. A heat spreader lid is bonded with the semiconductor die by reflowing the first bonding layer. A composite thermal interface material (TIM) structure is formed between the heat spreader lid and the semiconductor die during the bonding. The composite TIM structure includes the first bonding layer and the polymer particles embedded in the first bonding layer.

A bond tip for thermocompression bonding a bottom surface includes a die contact area and a low surface energy material covering at least a portion of the bottom surface. The low surface energy material may cover substantially all of the bottom surface, or only a peripheral portion surrounding the die contact area. The die contact area may be recessed with respect to the peripheral portion a depth at least as great as a thickness of a semiconductor die to be received in the recessed die contact area. A method of thermocompression bonding is also disclosed.

A bond tip for thermocompression bonding a bottom surface includes a die contact area and a low surface energy material covering at least a portion of the bottom surface. The low surface energy material may cover substantially all of the bottom surface, or only a peripheral portion surrounding the die contact area. The die contact area may be recessed with respect to the peripheral portion a depth at least as great as a thickness of a semiconductor die to be received in the recessed die contact area. A method of thermocompression bonding is also disclosed.

A package that includes a first integrated device comprising a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device comprising a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device through the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device.

A package that includes a first integrated device comprising a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device comprising a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device through the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device.

A wafer stack structure includes an interlayer, a first wafer, and a second wafer. The interlayer has a first surface and a second surface opposite to the first surface. The intermediate layer includes a dielectric material layer and a redistribution layer embedded in the dielectric material layer. The first wafer is disposed on the first surface of the interlayer. The second wafer is disposed on the second surface of the interlayer. The second wafer is electrically connected to the first wafer through the redistribution layer of the interlayer.

Disclosed is a method for manufacturing a semiconductor device which includes: a semiconductor chip; a substrate and/or another semiconductor chip; and an adhesive layer interposed therebetween. This method comprises the steps of: heating and pressuring a laminate having: the semiconductor chip; the substrate; the another semiconductor chip or a semiconductor wafer; and the adhesive layer by interposing the laminate with pressing members for temporary press-bonding to thereby temporarily press-bond the substrate and the another semiconductor chip or the semiconductor wafer to the semiconductor chip; and heating and pressuring the laminate by interposing the laminate with pressing members for main press-bonding, which are separately prepared from the pressing members for temporary press-bonding, to thereby electrically connect a connection portion of the semiconductor chip and a connection portion of the substrate or the another semiconductor chip.

A semiconductor structure includes a first die, second dies coupled to and on the first die, a dielectric layer on the first die and covering each second die, and through dielectric vias (TDVs) coupled to and on the first die. The first die includes a bonding dielectric layer and bonding features embedded in and leveled with the bonding dielectric layer. An array of second dies is arranged in a first region of the first die. Each second die includes a bonding dielectric layer and a bonding feature embedded in and leveled with the bonding dielectric layer. The bonding dielectric layer and the bonding feature of each second die are respectively bonded to those of the first die. The TDVs are laterally covered by the dielectric layer in a second region of the first die which is connected to the first region and arranged along a periphery of the first die.

A semiconductor structure including a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes a first bonding structure. The second semiconductor die is bonded to the first bonding structure of the first semiconductor die. The first bonding structure includes a first dielectric layer, a second dielectric layer covering the first dielectric layer, and first conductors embedded in the first dielectric layer and the second dielectric layer, wherein each of the first conductors includes a first conductive barrier layer covering the first dielectric layer and a first conductive pillar disposed on the first conductive barrier layer, and the first conductive pillars are in contact with the second dielectric layer.