A package structure includes a semiconductor die, a redistribution circuit structure, and a metallization element. The semiconductor die has an active side and an opposite side opposite to the active side. The redistribution circuit structure is disposed on the active side and is electrically coupled to the semiconductor die. The metallization element has a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side.

A package comprising a substrate, a first integrated device and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects, a solder resist layer, and a plurality of periphery interconnects located over the solder resist layer. The first integrated device is coupled to the substrate. The second integrated device is coupled to the substrate. The second integrated device is configured to be electrically coupled to the first integrated device through the plurality of periphery interconnects.

An electronic module has a first substrate 11, an electronic element 13, 23 disposed on one side of the first substrate 11, a second substrate 21 disposed on one side of the electronic element 13, 23, a first coupling body 210 disposed between the first substrate 11 and the second substrate 21, a second coupling body 220 disposed between the first substrate 11 and the second substrate 21, and shorter than the first coupling body 210, and a sealing part 90 which seals at least the electronic element. The first coupling body 210 is not electrically connected to the electronic element. The second coupling body 220 is electrically connected to the electronic element 13, 23.

An embodiment of the present application discloses an optical fingerprint identification apparatus and an electronic device, which can improve performance of the optical fingerprint identification apparatus. The optical fingerprint identification apparatus includes: a light detection array; a filter layer, disposed above the light detection array, where the filter layer is integrated with the light detection array in a photosensor chip; a first light blocking layer formed above the filter layer, where the first light blocking layer is provided with a plurality of light passing holes; and a first microlens array disposed above the first light blocking layer, where the first microlens array is configured to converge the optical signal to the plurality of light passing holes of the first light blocking layer, and the optical signal is transmitted to the light detection array through the plurality of light passing holes of the first light blocking layer.

A connection terminal unit that can be appropriately connected to terminal connection portions of a semiconductor module including a semiconductor element and that can reduce a projection area when seen in a direction orthogonal to a direction along a chip surface is realized. Connection terminal unit includes plurality of connection terminals facing and connected to plurality of terminal connection portions of semiconductor module, and terminal mold portion holding connection terminals. Terminal mold portion has abutment portion that abuts against semiconductor module or base material holding semiconductor module. Abutment portion has vertical abutment portion that abuts against semiconductor module or base material from vertical direction that is a direction in which connection terminals face terminal connection portions, and side abutment portion that abuts against semiconductor module or base material from at least two directions that are different from each other and intersect with vertical direction.

A package comprising a substrate, a first integrated device and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects, a solder resist layer, and a plurality of periphery interconnects located over the solder resist layer. The first integrated device is coupled to the substrate. The second integrated device is coupled to the substrate. The second integrated device is configured to be electrically coupled to the first integrated device through the plurality of periphery interconnects.

A package device preventing solder overflow provides a space or structure to limit the location of the solder when dispensing the solder. The package device includes a die, an anti-overflow layer, a first pin, a second pin, and a package body. The die has an electrode pad. The anti-overflow layer is disposed on a top surface of the electrode pad and has an opening to expose the top surface of the electrode pad. The first pin is connected to the die. The second pin is soldered to the electrode pad of the die through the opening of the anti-overflow layer. The package body covers the die.

A package structure includes a semiconductor die, a redistribution circuit structure, and a metallization element. The semiconductor die has an active side and an opposite side opposite to the active side. The redistribution circuit structure is disposed on the active side and is electrically coupled to the semiconductor die. The metallization element has a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side.

An exemplary semiconductor device can comprise a die, a redistribution structure (RDS), an interconnect, a conductive strap, an encapsulant, and an EMI shield. The redistribution structure can comprise an RDS top surface coupled to the die bottom side. The interconnect can be coupled to the RDS bottom surface. The conductive strap can be coupled to the RDS, and can comprise a strap inner end coupled to the RDS bottom surface, and a strap outer end located lower than the RDS bottom surface. The encapsulant can encapsulate the conductive strap and the RDS bottom surface. The EMI shield can cover and contact the encapsulant sidewall and the strap outer end. Other examples and related methods are also disclosed herein.

A three dimensional integrated circuit (3D-IC) module socket system includes an integrated Fan-Out (InFO) adapter having one or more integrated passive devices (IPDs) embedded in the InFO adapter. The InFO adapter is also integrated into the 3D-IC module socket system by stacking the InFO adapter between a socket and a SoW package. The InFO adapter with embedded IPDs allows for more planar area of the SoW package to be available for interfacing the socket and provides a short distance between the embedded IPDs and computing dies of the SoW package which enhances a power distribution network (PDN) performance and improves current handling of the 3D-IC module socket system.