Patent classifications
H01L2224/75821
Arrangement and method for joining at least two joining partners
An arrangement for joining two joining members includes a first part having a support surface, a first carrier element configured to carry at least one foil, a transportation unit configured to arrange the first carrier element such that the foil is arranged above the support surface in a vertical direction, and a second part configured to exert pressure to a joining stack, when the joining stack is arranged on the support surface. The joining stack includes a first joining member arranged on the support surface, a second joining member, and an electrically conductive connection layer arranged between the joining members. When pressure is exerted on the joining stack, the foil is arranged between the second part and the joining stack and is pressed onto the joining stack and the joining stack is pressed onto the first part, compressing the connection layer and forming a bond between the joining members.
METHOD FOR MANUFACTURING DISPLAY DEVICE AND APPARATUS FOR MANUFACTURING DISPLAY DEVICE
A method for manufacturing a display device includes preparing a display device including a display panel including a first alignment mark and a first circuit board including a second alignment mark and on one end of the display panel, disposing the display device on a stage including a base mark, setting the base mark as a reference mark in consideration of a relative position relation between the first alignment mark and the base mark by sensing the first alignment mark and the base mark, and determining a bending state of the display device by sensing the base mark and the second alignment mark and identifying a position relation between the base mark and the second alignment mark.
SINTERING DEVICE
Sintering device (10) for sintering at least one electronic assembly (BG), having a lower die (20) and an upper die (30) which is slidable towards the lower die (20), or a lower die (20) which is slidable towards the upper die (30), wherein the lower die (20) forms a support for the assembly (BG) to be sintered and the upper die (30) comprises a receptacle which receives a pressure pad (32) for exerting pressure directed towards the lower die (20) and which comprises a delimitation wall (34) which laterally surrounds the pressure pad (32), and wherein the delimitation wall (34) has an outer delimitation wall (34a) and an inner delimitation wall (34b) which is surrounded in an adjacent manner by the outer delimitation wall (34a), and wherein the inner delimitation wall (34b) is mounted so as to be slidable towards the outer delimitation wall (34a) and, when pressure in the direction of the upper die (30) is exerted on the pressure pad (32), is mounted so as to be slid in the direction of the lower die (20), whereby, following the placing of the inner delimitation wall (34b) on the lower die (20), the pressure pad (32) is displaceable in the direction of the lower die (20).
SINTERING TOOL AND METHOD FOR SINTERING AN ELECTRONIC SUBASSEMBLY
Sintering tool (10) with a cradle for receiving an electronic subassembly (BG) to be sintered, characterized by at least one support bracket (20), arranged at two locations opposite the cradle, for fixing a protective film (30) covering the electronic subassembly (BG).
Panel level packaging for devices
Panel level packaging (PLP) with high accuracy and high scalability is disclosed. The PLP employs an alignment carrier with a low coefficient of expansion which is configured with die regions having local die alignment marks. For example, local die alignment marks are provided for each die attach region. Depending on the size of the panel, it may be segmented into blocks, each with die regions with local die alignment marks. In addition, a block includes an alignment die region configured for attaching an alignment die. Linear and non-linear positional errors are reduced due to local die alignment marks and alignment dies. The use of local die alignment marks and alignment dies results in increase yields as well as scaling, thereby improving throughput and decreasing overall costs.
SOLDERLESS INTERCONNECT FOR SEMICONDUCTOR DEVICE ASSEMBLY
Semiconductor device assemblies with solderless interconnects, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly includes a first conductive pillar extending from a semiconductor die and a second conductive pillar extending from a substrate. The first conductive pillar may be connected to the second conductive pillar via an intermediary conductive structure formed between the first and second conductive pillars using an electroless plating solution injected therebetween. The first and second conductive pillars and the intermediary conductive structure may include copper as a common primary component, exclusive of an intermetallic compound (IMC) of a soldering process. A first sidewall surface of the first conductive pillar may be misaligned with respect to a corresponding second sidewall surface of the second conductive pillar. Such interconnects formed without IMC may improve electrical and metallurgical characteristics of the interconnects for the semiconductor device assemblies.
Mask changing unit for laser bonding apparatus
Provided is a mask changing unit for a laser bonding apparatus, and more particularly, a mask changing unit for a laser bonding apparatus, wherein the mask changing unit supplies or changes a mask to or in the laser bonding apparatus for bonding a semiconductor chip to a substrate by using a laser beam. The mask changing unit for a laser bonding apparatus, a plurality of masks that are used in performing laser bonding of a semiconductor chip to a substrate while the semiconductor chip is being pressed may be easily supplied to the laser bonding apparatus or changed in the laser bonding apparatus.
Apparatus, control method and control device of semiconductor packaging
In one aspect of the invention, a semiconductor packaging apparatus is provided and comprises: a bonding device for bonding a component to a substrate; a motor for driving the bonding device to operate according to a predetermined motion trajectory; a position sensor for detecting a position of the bonding device at a specific time point and generating a position signal; a motion control unit comprising a path planner for generating a position-time command for the bonding device according to a bonding process requirement, the motion control unit being configured to enable the path planner to update the position-time command based on a touch information between the component and the substrate. In a further aspect of the invention, a control algorithm for the semiconductor packaging apparatus to identify and generate the touch information is also provided, and the process control flow is optimized using the touch information.
Die bond head apparatus with die holder motion table
A die bond head apparatus has a die bond head body coupled to a die bond head motion table, a die holder motion table mounted on the die bond head body and a die holder which is operative in use to secure a semiconductor die to a substrate. The die holder is positionable by the die holder motion table independently of the die bond head motion table.
Solderless interconnect for semiconductor device assembly
Semiconductor device assemblies with solderless interconnects, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly includes a first conductive pillar extending from a semiconductor die and a second conductive pillar extending from a substrate. The first conductive pillar may be connected to the second conductive pillar via an intermediary conductive structure formed between the first and second conductive pillars using an electroless plating solution injected therebetween. The first and second conductive pillars and the intermediary conductive structure may include copper as a common primary component, exclusive of an intermetallic compound (IMC) of a soldering process. A first sidewall surface of the first conductive pillar may be misaligned with respect to a corresponding second sidewall surface of the second conductive pillar. Such interconnects formed without IMC may improve electrical and metallurgical characteristics of the interconnects for the semiconductor device assemblies.