A method includes, receiving a layout design of at least part of an electronic module, the design specifying at least (i) an electronic device coupled to at least a substrate, and (ii) an electrical trace that is connected to the electronic device and has a designed route. A digital input, which represents at least part of an actual electronic module that was manufactured in accordance with the layout design but without at least a portion of the electrical trace, is received. An error in coupling the electronic device to the substrate, relative to the layout design, is estimated based on the digital input. An actual route that corrects the estimated error, is calculated for at least the portion of the electrical trace. At least the portion of the electrical trace is formed on the substrate of the actual electronic module, along the actual route instead of the designed route.

A method includes, receiving a layout design of at least part of an electronic module, the design specifying at least (i) an electronic device coupled to at least a substrate, and (ii) an electrical trace that is connected to the electronic device and has a designed route. A digital input, which represents at least part of an actual electronic module that was manufactured in accordance with the layout design but without at least a portion of the electrical trace, is received. An error in coupling the electronic device to the substrate, relative to the layout design, is estimated based on the digital input. An actual route that corrects the estimated error, is calculated for at least the portion of the electrical trace. At least the portion of the electrical trace is formed on the substrate of the actual electronic module, along the actual route instead of the designed route.

The disclosure relates to systems, and methods for improving connectivity of embedded components. Specifically, the disclosure relates to systems and methods for using additive manufacturing to improve connectivity of embedded components with the host structure and/or other embedded components by selectably bridging the gap naturally formed due to manufacturing variation and built in tolerances, between the embedded components or devices and the host structure, and between one embedded component and a plurality of other embedded components.

A method of forming a semiconductor structure on a wafer includes depositing a polymer layer on the wafer in a wafer-level packaging process, forming at least one wafer-level packaging structure in the polymer layer using a direct writing process that alters a chemical property of portions of the polymer layer that have been directly written to, and removing portions of the polymer layer that have not been written to by the direct writing process revealing the at least one wafer-level packaging structure. In some embodiments, the direct writing process is a two-photon polymerization process that uses a femtosecond laser in combination with a pair of galvanometric laser scanners to solidify portions of the polymer layer to form the wafer-level packaging structure.

Multichip technology, where several discrete chips are assembled or are fabricated on a single substrate can offer many advantages, including better scaling and better yield. However, existing methods of connecting the individual chips on a substrate, leaves these devices operating at much slower rates than their individual chips are capable of operating. Disclosed are systems and methods for fast interconnect structures between chips in a multi die setup, where density, bandwidth, power consumption and other interconnect operating parameters are improved.

A method for producing electronic devices includes fixing a die that includes an electronic component with integral contacts to a dielectric substrate. After fixing the die, a conductive trace is printed over both the dielectric substrate and at least one of the integral contacts, so as to create an ohmic connection between the conductive trace on the substrate and the electronic component.

The present invention provides an exposure apparatus which exposes a substrate, comprising a measurement unit configured to measure a height of the substrate at each of a plurality of measurement points, and a control unit configured to control the height of the substrate based on measurement results obtained by the measurement unit, and control an operation to arrange a shot region of the substrate in a first position and expose the shot region, wherein the shot region includes a plurality of partial regions, and the control unit causes the measurement unit to measure the height of the substrate by arranging the shot region in a second position different from the first position so that the number of measurement points arranged in the plurality of partial regions is larger than that when arranging the shot region in the first position.

The present invention provides an exposure apparatus which exposes a substrate, comprising a measurement unit configured to measure a height of the substrate at each of a plurality of measurement points, and a control unit configured to control the height of the substrate based on measurement results obtained by the measurement unit, and control an operation to arrange a shot region of the substrate in a first position and expose the shot region, wherein the shot region includes a plurality of partial regions, and the control unit causes the measurement unit to measure the height of the substrate by arranging the shot region in a second position different from the first position so that the number of measurement points arranged in the plurality of partial regions is larger than that when arranging the shot region in the first position.