Patent classifications
H01L2224/80201
Method of fabrication of an integrated spiral inductor having low substrate loss
After finishing of the front side CMOS manufacturing process, the silicon wafer is permanently bonded with its front side onto a carrier wafer. The carrier wafer is a high resistivity silicon wafer or a wafer of a dielectric or of a ceramic material. The silicon substrate of the device wafer is thinned from the back side such that the remaining silicon thickness is only a few micrometers. In the area dedicated to a spiral inductor, the substrate material is entirely removed by a masked etching process and the resulting gap is filled with a dielectric material. A spiral inductor coil is formed on the backside of the wafer on top of the dielectric material. The inductor coil is connected to the CMOS circuits on the front side by through-silicon vias.
Method of fabrication of an integrated spiral inductor having low substrate loss
After finishing of the front side CMOS manufacturing process, the silicon wafer is permanently bonded with its front side onto a carrier wafer. The carrier wafer is a high resistivity silicon wafer or a wafer of a dielectric or of a ceramic material. The silicon substrate of the device wafer is thinned from the back side such that the remaining silicon thickness is only a few micrometers. In the area dedicated to a spiral inductor, the substrate material is entirely removed by a masked etching process and the resulting gap is filled with a dielectric material. A spiral inductor coil is formed on the backside of the wafer on top of the dielectric material. The inductor coil is connected to the CMOS circuits on the front side by through-silicon vias.
Semiconductor Package and Method of Forming Same
A method of forming a semiconductor package includes attaching a first package component to a first carrier; attaching a second package component to the first carrier, the second package component laterally displaced from the first package component; attaching a third package component to the first package component, the third package component being electrically connected to the first package component; removing the first carrier from the first package component and the second package component; after removing the first carrier, performing a first circuit probe test on the second package component to obtain first test data of the second package component; and comparing the first test data of the second package component with prior data of the second package component.
Small pitch integrated knife edge temporary bonding microstructures
A temporary bond method and apparatus for allowing wafers, chips or chiplets. To be tested, the temporary bond method and apparatus comprising: a temporary connection apparatus having one of more knife-edged microstructures, wherein the temporary connection apparatus serves, in use, as a probe device for probing the chiplets, each chiplet including a die having one or more flat contact pads which mate with the one of more knife-edged microstructures of the temporary connection apparatus; a press apparatus for applying pressure between the one or more flat contact pads on the chiplet with the one of more knife-edged microstructures of the temporary connection apparatus thereby forming a temporary bond between the temporary connection pad with the knife-edged microstructure in contact with the one or more flat wafer pads; the press being able to apply a pressure to maintain the temporary bond connection during or prior to testing of the chiplet.
Packaged multi-chip semiconductor devices and methods of fabricating same
A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.
Method for producing structure, and structure
This method for producing a structure wherein base materials are bonded by atomic diffusion comprises: a step for applying a liquid resin on the base material; a step for smoothing the surface of the liquid resin by surface tension; a step for forming a resin layer by curing; a step for forming a metal thin film on the resin layer; a step for forming a metal thin film on the base material; and a step for bringing the metal thin film of the base material and the metal thin film of the base material into close contact with each other, thereby bonding the metal thin film of the resin layer and the metal thin film of the base material with each other by atomic diffusion.
Method for producing structure, and structure
This method for producing a structure wherein base materials are bonded by atomic diffusion comprises: a step for applying a liquid resin on the base material; a step for smoothing the surface of the liquid resin by surface tension; a step for forming a resin layer by curing; a step for forming a metal thin film on the resin layer; a step for forming a metal thin film on the base material; and a step for bringing the metal thin film of the base material and the metal thin film of the base material into close contact with each other, thereby bonding the metal thin film of the resin layer and the metal thin film of the base material with each other by atomic diffusion.
Integrated circuit package and method of forming thereof
A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.
APPARATUS FOR BONDING SUBSTRATES HAVING A SUBSTRATE HOLDER WITH HOLDING FINGERS AND METHOD OF BONDING SUBSTRATES
A substrate bonding apparatus includes a substrate susceptor to support a first substrate, a substrate holder over the substrate susceptor to hold a second substrate, the substrate holder including a plurality of independently moveable holding fingers, and a chamber housing to accommodate the substrate susceptor and the substrate holder.
APPARATUS FOR BONDING SUBSTRATES HAVING A SUBSTRATE HOLDER WITH HOLDING FINGERS AND METHOD OF BONDING SUBSTRATES
A substrate bonding apparatus includes a substrate susceptor to support a first substrate, a substrate holder over the substrate susceptor to hold a second substrate, the substrate holder including a plurality of independently moveable holding fingers, and a chamber housing to accommodate the substrate susceptor and the substrate holder.