H01L2224/80379

CHEMICAL BONDING METHOD, PACKAGE-TYPE ELECTRONIC COMPONENT, AND HYBRID BONDING METHOD FOR ELECTRONIC DEVICE

Substrates that are bonding targets are bonded in ambient atmosphere via bonding films, including oxides, formed on bonding faces of the substrates. The bonding films, which are metal or semiconductor thin films formed by vacuum film deposition and at least the surfaces of which are oxidized, are formed into the respective smooth faces of two substrates having the smooth faces that serve as the bonding faces. The bonding films are exposed to a space that contains moisture, and the two substrates are overlapped in the ambient atmosphere such that the surfaces of the bonding films are made to be hydrophilic and the surfaces of the bonding films contact one another. Through this, a chemical bond is generated at the bonded interface, and thereby the two substrates are bonded together in the ambient atmosphere. The bonding strength γ can be improved by heating the bonded substrates at a temperature.

Heat spreading layer integrated within a composite IC die structure and methods of forming the same

A heat spreading material is integrated into a composite die structure including a first IC die having a first dielectric material and a first electrical interconnect structure, and a second IC die having a second dielectric material and a second electrical interconnect structure. The composite die structure may include a composite electrical interconnect structure comprising the first interconnect structure in direct contact with the second interconnect structure at a bond interface. The heat spreading material may be within at least a portion of a dielectric area through which the bond interface extends. The heat spreading material may be located within one or more dielectric materials surrounding the composite interconnect structure, and direct a flow of heat generated by one or more of the first and second IC dies.

Heat spreading layer integrated within a composite IC die structure and methods of forming the same

A heat spreading material is integrated into a composite die structure including a first IC die having a first dielectric material and a first electrical interconnect structure, and a second IC die having a second dielectric material and a second electrical interconnect structure. The composite die structure may include a composite electrical interconnect structure comprising the first interconnect structure in direct contact with the second interconnect structure at a bond interface. The heat spreading material may be within at least a portion of a dielectric area through which the bond interface extends. The heat spreading material may be located within one or more dielectric materials surrounding the composite interconnect structure, and direct a flow of heat generated by one or more of the first and second IC dies.

Semiconductor Package and Method of Forming Same

A method of forming a semiconductor package includes attaching a first package component to a first carrier; attaching a second package component to the first carrier, the second package component laterally displaced from the first package component; attaching a third package component to the first package component, the third package component being electrically connected to the first package component; removing the first carrier from the first package component and the second package component; after removing the first carrier, performing a first circuit probe test on the second package component to obtain first test data of the second package component; and comparing the first test data of the second package component with prior data of the second package component.

Packaged multi-chip semiconductor devices and methods of fabricating same

A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

Packaged multi-chip semiconductor devices and methods of fabricating same

A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

Semiconductor package

A semiconductor package is provided. The semiconductor package includes a first conductive layer, a plurality of first conductive pads, a plurality of second conductive pads, and a first dielectric layer. The first conductive pads are electrically connected to the first conductive layer. The second conductive pads are electrically disconnected from the first conductive layer.

Semiconductor package

A semiconductor package is provided. The semiconductor package includes a first conductive layer, a plurality of first conductive pads, a plurality of second conductive pads, and a first dielectric layer. The first conductive pads are electrically connected to the first conductive layer. The second conductive pads are electrically disconnected from the first conductive layer.

Fabricating method of semiconductor device with exposed input/output pad in recess

A fabricating method of a semiconductor device is provided. A temporary semiconductor structure is provided. The temporary semiconductor structure includes a temporary substrate and a conductive layer, the temporary substrate has a first surface, the conductive layer is disposed on the first surface of the temporary substrate, and the conductive layer includes one or more first trace. Then, a recess is formed in the temporary semiconductor structure to form a first semiconductor structure and a first substrate. The recess penetrates through the first substrate and expose the one or more first trace. Thereafter, an input/output pad is formed in the recess and on the one or more first trace.

Fabricating method of semiconductor device with exposed input/output pad in recess

A fabricating method of a semiconductor device is provided. A temporary semiconductor structure is provided. The temporary semiconductor structure includes a temporary substrate and a conductive layer, the temporary substrate has a first surface, the conductive layer is disposed on the first surface of the temporary substrate, and the conductive layer includes one or more first trace. Then, a recess is formed in the temporary semiconductor structure to form a first semiconductor structure and a first substrate. The recess penetrates through the first substrate and expose the one or more first trace. Thereafter, an input/output pad is formed in the recess and on the one or more first trace.