Patent classifications
H01L2224/80416
Substrate with electronic component embedded therein
A substrate with an electronic component embedded therein includes: a core structure having a cavity; a metal layer disposed on a bottom surface of the cavity of the core structure; and an electronic component disposed on the metal layer in the cavity of the core structure. The substrate with the electronic component embedded therein has an excellent heat dissipation effect.
Substrate with electronic component embedded therein
A substrate with an electronic component embedded therein includes: a core structure having a cavity; a metal layer disposed on a bottom surface of the cavity of the core structure; and an electronic component disposed on the metal layer in the cavity of the core structure. The substrate with the electronic component embedded therein has an excellent heat dissipation effect.
SUBSTRATE WITH ELECTRONIC COMPONENT EMBEDDED THEREIN
A substrate with an electronic component embedded therein includes: a core structure having a cavity; a metal layer disposed on a bottom surface of the cavity of the core structure; and an electronic component disposed on the metal layer in the cavity of the core structure. The substrate with the electronic component embedded therein has an excellent heat dissipation effect.
SUBSTRATE WITH ELECTRONIC COMPONENT EMBEDDED THEREIN
A substrate with an electronic component embedded therein includes: a core structure having a cavity; a metal layer disposed on a bottom surface of the cavity of the core structure; and an electronic component disposed on the metal layer in the cavity of the core structure. The substrate with the electronic component embedded therein has an excellent heat dissipation effect.
CHIP-TO-CHIP STACKING BY USE OF NICKEL TIN METALLIZATION STACKS AND DIFFUSION SOLDERING
A method for fabricating a semiconductor device includes: providing a substrate layer stack including a substrate with a metallic upper surface, a first Ni containing layer disposed on the substrate, and a first Sn layer on the first Ni containing layer; depositing a first semiconductor layer stack on the first Sn layer and that includes a first NiP layer, a first semiconductor die disposed on the first NiP layer, and a second NiP layer disposed on the first semiconductor die; depositing a second semiconductor layer stack on the first semiconductor layer stack and that includes a second Sn layer, a second Ni containing layer disposed on the second Sn layer, and a second semiconductor die disposed on the second Ni containing layer; and performing a diffusion soldering process for connecting the first semiconductor layer stack to the substrate and the second semiconductor layer stack to the first semiconductor layer stack.