Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. The fill layer is composed of noble metal (such as copper) and active metal (such as Zn). Then the fill metal layer is turned into a metal alloy after annealing. A dealloying is performed to the metal alloy to remove the active metal from the metal alloy while the noble metal remains to self-assemble into porous (nanoporous) structure metal. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using dielectric-to-dielectric direct bonding techniques, with the fill nanoporous metal layer in the recesses in one of the first and second interconnect structures. After the following batch annealing, the fill nanoporous metal layer turns into pure bulk metal same as conductive interconnect structures due to the heat expansion of conductive interconnect structures and nanoporous metal densification.

Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.

Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.

A package structure includes a first die, a second die, an insulation structure, a through via, a dielectric layer and a redistribution layer. The second die is electrically bonded to the first die. The insulation structure is disposed on the first die and laterally surrounds the second die. The through via penetrates through the insulation structure to electrically connect to the first die. The through via includes a first barrier layer and a conductive post on the first barrier layer. The dielectric layer is on the second die and the insulation structure. The redistribution layer is embedded in the dielectric layer and electrically connected to the through via. The redistribution layer includes a second barrier layer and a conductive layer on the second barrier layer. The conductive layer of the redistribution layer is in contact with the conductive post of the through via.

An electronic circuit module. The module has a multilayered LTCC circuit carrier made of structured inorganic substrate layers, which have electrical and/or thermal conduction structures for electrical and/or thermal conduction, at least one electronic component, which is arranged on a first side and/or an opposite second side of the LTCC circuit carrier, and at least one SiC power semiconductor. The at least one SiC power semiconductor is embedded in the multilayered LTCC circuit carrier and enclosed at least on three sides by the multilayered LTCC circuit carrier. Connection contacts of the SiC power semiconductor contact the electrical and/or thermal conduction structures of the LTCC circuit carrier.

A connection structural body includes: a first connection terminal including a first opposing surface; a first roughened-surface copper metal film formed on the first opposing surface; a second connection terminal including a second opposing surface facing the first opposing surface; and a second roughened-surface copper metal film formed on the second opposing surface and bonded to the first roughened-surface copper metal film. The first roughened-surface copper metal film includes a structure in which first deposits of copper are piled over one another on the first opposing surface. The second roughened-surface copper metal film includes a structure in which second deposits of copper are piled over one another on the second opposing surface. A bonded portion of the first and second roughened-surface copper metal films includes a structure in which the first deposits and the second deposits are piled such that the bonded portion includes pores.

Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.

Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.

A package structure includes first and second dies, an insulation structure, a through via, a dielectric layer and a redistribution layer. The second die electrically bonded to the first die includes a through substrate via. The insulation structure is disposed on the first die and laterally surrounds the second die. The through via penetrates through the insulation structure to electrically connect to the first die. The dielectric layer is disposed on the second die and the insulation structure. The redistribution layer is embedded in the dielectric layer and electrically connected to the through via. The redistribution layer includes a first barrier layer and a conductive layer on the first barrier layer. The through substrate via is electrically connected to the redistribution layer, and the conductive layer is in contact with a conductive post of the through via and separated from the through substrate via by the first barrier layer therebetween.

Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.