An integrated circuit includes a first chip bonded to a second chip. The first chip includes gate all around transistors on a substrate. The first chip includes backside conductive vias extending through the substrate to the gate all around transistors. The second chip includes electronic circuitry electrically connected to the transistors by the backside conductive vias.

An inertial sensor includes a support substrate, a sensor main body supported by the support substrate, and a bonding member that is located between the support substrate and the sensor main body and bonds the sensor main body to the support substrate. The sensor main body includes a substrate bonded to the support substrate via the bonding member and a capacitance-type sensor device provided at a side of the substrate opposite to the support substrate. The substrate has a side surface, a first principal surface facing the support substrate, and a recessed step section that is located between the side surface and the first principal surface and connects the side surface to the first principal surface. The bonding member extends along the first principal surface and the step section.

An inertial sensor includes a support substrate, a sensor main body supported by the support substrate, and a bonding member that is located between the support substrate and the sensor main body and bonds the sensor main body to the support substrate. The sensor main body includes a substrate bonded to the support substrate via the bonding member and a capacitance-type sensor device provided at a side of the substrate opposite to the support substrate. The substrate has a side surface, a first principal surface facing the support substrate, and a recessed step section that is located between the side surface and the first principal surface and connects the side surface to the first principal surface. The bonding member extends along the first principal surface and the step section.

A memory array and single-crystal circuitry are provided by wafer bonding (e.g., adhesive wafer bonding or anodic wafer bonding) in the same integrated circuit and interconnected by conductors of an interconnect layer. Additional circuitry or memory arrays may be provided by additional wafer bonds and electrically connected by interconnect layers at the wafer bonding interface. The memory array may include storage or memory transistors having single-crystal epitaxial silicon channel material.

A memory array and single-crystal circuitry are provided by wafer bonding (e.g., adhesive wafer bonding or anodic wafer bonding) in the same integrated circuit and interconnected by conductors of an interconnect layer. Additional circuitry or memory arrays may be provided by additional wafer bonds and electrically connected by interconnect layers at the wafer bonding interface. The memory array may include storage or memory transistors having single-crystal epitaxial silicon channel material.

A method of producing a bonded chip stack is described. A first nanofluidic device chip having a first through-wafer via is formed. A second nanofluidic device chip having a second through-wafer via is formed. The first nanofluidic device chip and the second nanofluidic device chip are washed with a detergent solution. A first surface of the first nanofluidic device chip and a second surface of the second nanofluidic device chip are activated by treating the first surface and the second surface with an activation solution. The first nanofluidic device chip and the second nanofluidic device chip are arranged in a stack. The first through-wafer via is aligned with the second through-wafer via in a substantially straight line. The stack of first and second nanofluidic device chips is subjected to annealing conditions.

An inertial sensor includes a support substrate, a sensor main body supported by the support substrate, and a bonding member that is located between the support substrate and the sensor main body and bonds the sensor main body to the support substrate. The sensor main body includes a substrate bonded to the support substrate via the bonding member and a capacitance-type sensor device provided at a side of the substrate opposite to the support substrate. The substrate has a side surface, a first principal surface facing the support substrate, and a recessed step section that is located between the side surface and the first principal surface and connects the side surface to the first principal surface. The bonding member extends along the first principal surface and the step section.

An inertial sensor includes a support substrate, a sensor main body supported by the support substrate, and a bonding member that is located between the support substrate and the sensor main body and bonds the sensor main body to the support substrate. The sensor main body includes a substrate bonded to the support substrate via the bonding member and a capacitance-type sensor device provided at a side of the substrate opposite to the support substrate. The substrate has a side surface, a first principal surface facing the support substrate, and a recessed step section that is located between the side surface and the first principal surface and connects the side surface to the first principal surface. The bonding member extends along the first principal surface and the step section.

A method of producing a bonded chip stack is described. A first nanofluidic device chip having a first through-wafer via is formed. A second nanofluidic device chip having a second through-wafer via is formed. The first nanofluidic device chip and the second nanofluidic device chip are washed with a detergent solution. A first surface of the first nanofluidic device chip and a second surface of the second nanofluidic device chip are activated by treating the first surface and the second surface with an activation solution. The first nanofluidic device chip and the second nanofluidic device chip are arranged in a stack. The first through-wafer via is aligned with the second through-wafer via in a substantially straight line. The stack of first and second nanofluidic device chips is subjected to annealing conditions.

Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.