Patent classifications
H01L2224/81065
Structures and methods for low temperature bonding using nanoparticles
A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF
There is provided semiconductor devices and methods of forming the same, the semiconductor devices including: a first semiconductor element having a first electrode; a second semiconductor element having a second electrode; a Sn-based micro-solder bump formed on the second electrode; and a concave bump pad including the first electrode opposite to the micro-solder bump, where the first electrode is connected to the second electrode via the micro-solder bump and the concave bump pad.
Method for temporarily fastening a semiconductor chip to a surface, method for producing a semiconductor component and semiconductor component
In an embodiment a method for producing a semiconductor component comprising at least one semiconductor chip mounted on a surface, wherein the semiconductor chip is fixed on the surface by applying a solder compound to an assembling surface of the semiconductor chip, applying a metallic adhesive layer to a side of the solder compound facing away from the assembling surface, preheating the surface to a first temperature T1, bringing the metallic adhesive layer into mechanical contact in a solid state with the preheated surface, the metallic adhesive layer at least partially melting while it is brought into mechanical contact with the preheated surface, and subsequently cooling the surface to room temperature, the semiconductor chip being at least partially metallurgically bonded to the surface, and wherein the semiconductor chip is subsequently soldered to the surface to form a resulting solder connection.
Methods of bonding of semiconductor elements to substrates, and related bonding systems
A bonding system for bonding a semiconductor element to a substrate is provided. The bonding system includes a substrate oxide reduction chamber configured to receive a substrate. The substrate includes a plurality of first electrically conductive structures. The substrate oxide reduction chamber is configured to receive a reducing gas to contact each of the plurality of first electrically conductive structures. The bonding system also includes a substrate oxide prevention chamber for receiving the substrate after the reducing gas contacts the plurality of first electrically conductive structures. The substrate oxide prevention chamber has an inert environment when receiving the substrate. The bonding system also includes a reducing gas delivery system for providing a reducing gas environment during bonding of a semiconductor element to the substrate.
Method of forming thin die stack assemblies
Die stacks and methods of making die stacks with very thin dies are disclosed. The die surfaces remain flat within a 5 micron tolerance despite the thinness of the die and the process steps of making the die stack. A residual flux height is kept below 50% of the spacing distance between adjacent surfaces or structures, e.g. in the inter-die spacing.
Method of forming thin die stack assemblies
Die stacks and methods of making die stacks with very thin dies are disclosed. The die surfaces remain flat within a 5 micron tolerance despite the thinness of the die and the process steps of making the die stack. A residual flux height is kept below 50% of the spacing distance between adjacent surfaces or structures, e.g. in the inter-die spacing.
DIRECT BONDED HETEROGENEOUS INTEGRATION SILICON BRIDGE
A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.
Methods of bonding of semiconductor elements to substrates, and related bonding systems
A bonding system for bonding a semiconductor element to a substrate is provided. The bonding system includes a substrate oxide reduction chamber configured to receive a substrate. The substrate includes a plurality of first electrically conductive structures. The substrate oxide reduction chamber is configured to receive a reducing gas to contact each of the plurality of first electrically conductive structures. The bonding system also includes a substrate oxide prevention chamber for receiving the substrate after the reducing gas contacts the plurality of first electrically conductive structures. The substrate oxide prevention chamber has an inert environment when receiving the substrate. The bonding system also includes a reducing gas delivery system for providing a reducing gas environment during bonding of a semiconductor element to the substrate.
Methods of bonding of semiconductor elements to substrates, and related bonding systems
A bonding system for bonding a semiconductor element to a substrate is provided. The bonding system includes a substrate oxide reduction chamber configured to receive a substrate. The substrate includes a plurality of first electrically conductive structures. The substrate oxide reduction chamber is configured to receive a reducing gas to contact each of the plurality of first electrically conductive structures. The bonding system also includes a substrate oxide prevention chamber for receiving the substrate after the reducing gas contacts the plurality of first electrically conductive structures. The substrate oxide prevention chamber has an inert environment when receiving the substrate. The bonding system also includes a reducing gas delivery system for providing a reducing gas environment during bonding of a semiconductor element to the substrate.
Method for producing joined body, and joining material
Provided is a method for producing a joined body, the method including a first step of preparing a laminated body which includes a first member having a metal pillar provided on a surface thereof, a second member having an electrode pad provided on a surface thereof, and a joining material provided between the metal pillar and the electrode pad and containing metal particles and an organic compound, and a second step of heating the laminated body to sinter the joining material at a predetermined sintering temperature, in which the joining material satisfies the condition of the following Formula (I):
(M.sub.1−M.sub.2)/M.sub.1×100≥1.0 (I)
[in Formula (I), M.sub.1 represents a mass of the joining material when a temperature of the joining material reaches the sintering temperature in the second step, and M.sub.2 represents a non-volatile content in the joining material.]