Provided is a semiconductor chip mounting tape. The semiconductor chip mounting tape comprises a tape base film including first and second surfaces opposite to each other; and an adhesive film including a third surface facing the first surface of the tape base film, and a fourth surface opposite to the third surface, wherein the adhesive film includes a plurality of voids therein, and the fourth surface of the adhesive film may be adhered to a semiconductor chip.

A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

Provided is a semiconductor chip mounting tape. The semiconductor chip mounting tape comprises a tape base film including first and second surfaces opposite to each other; and an adhesive film including a third surface facing the first surface of the tape base film, and a fourth surface opposite to the third surface, wherein the adhesive film includes a plurality of voids therein, and the fourth surface of the adhesive film may be adhered to a semiconductor chip.

Disclosed herein are techniques for reducing a variation in the planarity of a display device. In some embodiments, a method includes applying a first pressure to a top surface of a display device at a first temperature. The display device includes a backplane, a plurality of dies, and a plurality of fusible interconnections between the backplane and the plurality of dies. The first pressure is applied in a direction that is perpendicular to a plane of the backplane on which the plurality of dies are arranged. The first pressure and the first temperature are selected to cause the plurality of fusible interconnections to absorb variations in a planarity of the top surface of the display device.

A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

An article of manufacture is formed by preparing a first silicon-on-insulator (SOI) wafer with first bonding pads at a first top or back-end-of-line (BEOL) surface thereof, preparing a second SOI wafer with second bonding pads at a second BEOL surface thereof, and attaching the first and second SOI wafers by bonding their bonding pads together, thereby producing a sandwiched wafer with first and second bottom or front-end-of-line (FEOL) surfaces facing outward and with first and second BEOL surfaces facing each other near the midline of the sandwiched wafer. The first SOI wafer then is prepared for packaging by first removing the silicon substrate from the first FEOL surface to reveal a buried oxide (BOX) layer, then fabricating interconnects atop the BOX layer and forming input output pads atop the interconnects.

A process includes forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer including a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer. A resultant article of manufacture is also disclosed.

A die bonding apparatus comprising a first inert gas container having a first inert gas concentration, and a second inert gas container having a second inert gas concentration enclosed within the first inert gas container. The second inert gas concentration is higher than the first inert gas concentration. The die bonding apparatus further comprises a bond head located in the second inert gas container for receiving a die for bonding, and a third inert gas container having an inert gas environment that is separate from the first and second inert gas containers and where a substrate is locatable for die bonding. The bond head is operative to move the die between a first position within the second inert container and a second position within the third inert gas container to bond the die onto the substrate located in the third inert gas container.

A die bonding apparatus comprising a first inert gas container having a first inert gas concentration, and a second inert gas container having a second inert gas concentration enclosed within the first inert gas container. The second inert gas concentration is higher than the first inert gas concentration. The die bonding apparatus further comprises a bond head located in the second inert gas container for receiving a die for bonding, and a third inert gas container having an inert gas environment that is separate from the first and second inert gas containers and where a substrate is locatable for die bonding. The bond head is operative to move the die between a first position within the second inert container and a second position within the third inert gas container to bond the die onto the substrate located in the third inert gas container.

The present disclosure is directed to an apparatus having a bond head configured to heat and compress a semiconductor package assembly, and a bonding stage configured to hold the semiconductor package assembly, wherein the bonding stage comprises a ceramic material including silicon and either magnesium or indium.